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EP0639000
European procedure
Extract from the Register of European Patents
EP About this file: EP0639000
| EP0639000 - Flip-flop type amplifier circuit [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 07.05.1999 Database last updated on 05.08.2024 | Most recent event Tooltip | 07.05.1999 | No opposition filed within time limit | published on 23.06.1999 [1999/25] | Applicant(s) | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi Kanagawa 211 / JP | [N/P] |
| Former [1995/07] | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi, Kanagawa 211 / JP | Inventor(s) | 01 /
Kawashima, Shoichiro, c/o FUJITSU LIMITED Patent Department, 1015 Kamikodanaka, Nakahara-ku Kawasaki-shi, Kanagawa 211 / JP | [1995/07] | Representative(s) | Stebbing, Timothy Charles, et al Haseltine Lake LLP Lincoln House, 5th Floor 300 High Holborn London WC1V 7JH / GB | [N/P] |
| Former [1995/07] | Stebbing, Timothy Charles, et al Haseltine Lake & Co. Hazlitt House 28 Southampton Buildings Chancery Lane London WC2A 1AT / GB | Application number, filing date | 94111302.9 | 20.07.1994 | [1995/07] | Priority number, date | JP19930197101 | 09.08.1993 Original published format: JP 19710193 | [1995/07] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0639000 | Date: | 15.02.1995 | Language: | EN | [1995/07] | Type: | A3 Search report | No.: | EP0639000 | Date: | 25.10.1995 | Language: | EN | [1995/43] | Type: | B1 Patent specification | No.: | EP0639000 | Date: | 01.07.1998 | Language: | EN | [1998/27] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 05.09.1995 | Classification | IPC: | H03K3/037, H03K3/356 | [1995/07] | CPC: |
H03K3/037 (EP,US);
H03K5/00 (KR);
H03G3/00 (KR);
H03K3/356156 (EP,US);
H03K3/356182 (EP,US)
| Designated contracting states | DE, GB, IT [1998/08] |
| Former [1995/07] | DE, FR, GB, IT | Title | German: | Verstärkerschaltung des Flipflop-Typs | [1995/07] | English: | Flip-flop type amplifier circuit | [1995/07] | French: | Circuit amplificateur du type bascule | [1995/07] | Examination procedure | 18.04.1996 | Examination requested [1996/24] | 03.02.1997 | Despatch of a communication from the examining division (Time limit: M06) | 11.06.1997 | Reply to a communication from the examining division | 02.07.1997 | Despatch of a communication from the examining division (Time limit: M04) | 23.08.1997 | Reply to a communication from the examining division | 17.11.1997 | Despatch of communication of intention to grant (Approval: Yes) | 05.01.1998 | Communication of intention to grant the patent | 26.03.1998 | Fee for grant paid | 26.03.1998 | Fee for publishing/printing paid | Opposition(s) | 02.04.1999 | No opposition filed within time limit [1999/25] | Fees paid | Renewal fee | 25.07.1996 | Renewal fee patent year 03 | 23.07.1997 | Renewal fee patent year 04 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]US5196737 (OLMSTEAD JOHN A [US]) [A] 1 * column 2, line 61 - column 4, line 30; figure 2 *; | [A]US4627033 (HYSLOP ADIN E [US], et al) [A] 1 * column 5, line 28 - column 6, line 37; figure 6 *; | [A]EP0450454 (NAT SEMICONDUCTOR CORP [US]) [A] 1 * page 2, column 2, line 5 - page 3, column 3, line 12; figure 1; claim 1 * | Examination | - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 28, no. 4, September 1985, pages 1716-1718; "Latching-Node Clock Design in Half-VDD Bit-Line CMOS Sense Amplifier" |