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EP0627631
European procedure
Extract from the Register of European Patents
EP About this file: EP0627631
| EP0627631 - Analog autonomous test bus framework for testing integrated circuits on a printed circuit board [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 06.12.2002 Database last updated on 05.10.2024 | Most recent event Tooltip | 22.08.2008 | Change - applicant | published on 24.09.2008 [2008/39] | Applicant(s) | For all designated states Koninklijke Philips Electronics N.V. Groenewoudseweg 1 5621 BA Eindhoven / NL | [2008/39] |
| Former [2002/05] | For all designated states Koninklijke Philips Electronics N.V. Groenewoudseweg 1 5621 BA Eindhoven / NL | ||
| Former [1994/49] | For all designated states PHILIPS ELECTRONICS N.V. Groenewoudseweg 1 NL-5621 BA Eindhoven / NL | Inventor(s) | 01 /
Lee, Nai-Chi c/o Int. Octrooibureau B.V., Prof. Holstlaan 6 NL-5656 AA Eindhoven / NL | [1994/49] | Representative(s) | Rolfes, Johannes Gerardus Albertus Philips Intellectual Property & Standards P.O. Box 220 5600 AE Eindhoven / NL | [N/P] |
| Former [2000/13] | Rolfes, Johannes Gerardus Albertus INTERNATIONAAL OCTROOIBUREAU B.V., Prof. Holstlaan 6 5656 AA Eindhoven / NL | ||
| Former [1994/49] | Strijland, Wilfred INTERNATIONAAL OCTROOIBUREAU B.V., Prof. Holstlaan 6 NL-5656 AA Eindhoven / NL | Application number, filing date | 94201407.7 | 18.05.1994 | [1994/49] | Priority number, date | US19930066957 | 24.05.1993 Original published format: US 66957 | [1994/49] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0627631 | Date: | 07.12.1994 | Language: | EN | [1994/49] | Type: | A3 Search report | No.: | EP0627631 | Date: | 17.05.1995 | Language: | EN | [1995/20] | Type: | B1 Patent specification | No.: | EP0627631 | Date: | 30.01.2002 | Language: | EN | [2002/05] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 29.03.1995 | Classification | IPC: | G01R31/28, G06F11/22 | [1995/15] | CPC: |
G01R31/318558 (EP,US);
G01R31/2884 (EP,US);
G01R31/3167 (EP,US)
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| Former IPC [1994/49] | G01R31/28 | Designated contracting states | DE, FR, GB, IT [1994/49] | Title | German: | Analoge, selbstständige Prüfbusstruktur zum Testen integrierter Schaltungen auf einer gedruckten Leiterplatte | [1994/49] | English: | Analog autonomous test bus framework for testing integrated circuits on a printed circuit board | [1994/49] | French: | Structure de bus d'essai autonome et analogique pour tester des circuits intégrés sur une plaque à circuit imprimée | [1994/49] | Examination procedure | 17.11.1995 | Examination requested [1996/02] | 05.01.2000 | Despatch of a communication from the examining division (Time limit: M04) | 04.05.2000 | Reply to a communication from the examining division | 30.03.2001 | Despatch of communication of intention to grant (Approval: Yes) | 18.07.2001 | Communication of intention to grant the patent | 29.10.2001 | Fee for grant paid | 29.10.2001 | Fee for publishing/printing paid | Opposition(s) | 31.10.2002 | No opposition filed within time limit [2003/04] | Fees paid | Renewal fee | 31.05.1996 | Renewal fee patent year 03 | 02.06.1997 | Renewal fee patent year 04 | 02.06.1998 | Renewal fee patent year 05 | 31.05.1999 | Renewal fee patent year 06 | 31.05.2000 | Renewal fee patent year 07 | 31.05.2001 | Renewal fee patent year 08 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [DY]EP0434137 (PHILIPS NV [NL]) [DY] 1-9 * abstract * * page 3, line 36 - page 4, line 38; figures 1,2 *; | US5107208 [ ] (LEE NAI C [US]); | [Y] - K. D. PARKER ET AL., "Structure and metrology for an analog testability bus", PROCEEDINGS INTERNATIONAL TEST CONFERENCE 1993, (19930101), pages 309 - 322, XP000431465 [Y] 1-9 * page 310, column L, line 21 - column R, line 13 * * page 311, column L, line 31 - page 312, column R, line 16 * * figures 2,4 * | [A] - C. W. THATCHER ET AL., "Towards a test standard for board and system level mixed-signal interconnects", PROCEEDINGS INTERNATIONAL TEST CONFERENCE 1993, (19930101), pages 300 - 308, XP000437141 [A] 1-9 * page 304, column R, line 18 - line 25 * * page 305, column L, line 18 - line 22 * * page 306, column L, line 7 - line 30 * * figures 6,7 * | [PX] - N.-L. LEE, "A hierarchical analog test bus framework for testing mixed-signal intergrated circuits and printed circuit boards", JOURNAL OF ELECTRONIC TESTING, DORDRECHT NL, (199311), vol. 4, no. 4, pages 361 - 368 [PX] 1-9 |