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EP0632390
European procedure
Extract from the Register of European Patents
EP About this file: EP0632390
| EP0632390 - Processor circuit comprising a first processor, and system comprising the processor circuit and a second processor [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 30.03.2001 Database last updated on 20.12.2024 | Most recent event Tooltip | 30.03.2001 | No opposition filed within time limit | published on 16.05.2001 [2001/20] | Applicant(s) | For all designated states Koninklijke KPN N.V. Stationsplein 7 9726 AE Groningen / NL | [1998/49] |
| Former [1995/01] | For all designated states Koninklijke PTT Nederland N.V. P.O. Box 95321 NL-2509 CH The Hague / NL | Inventor(s) | 01 /
Vankan, Franciscus Anna Gerardus De Haar 10 NL-2261 XS Leidschendam / NL | 02 /
Pieterse, Rob C.v.d. Lindenstraat 2 F 24 NL-2042 CA Zandvoort / NL | [1995/01] | Application number, filing date | 94201639.5 | 09.06.1994 | [1995/01] | Priority number, date | NL19930001129 | 29.06.1993 Original published format: NL 9301129 | [1995/01] | Filing language | NL | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0632390 | Date: | 04.01.1995 | Language: | EN | [1995/01] | Type: | B1 Patent specification | No.: | EP0632390 | Date: | 24.05.2000 | Language: | EN | [2000/21] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 13.10.1994 | Classification | IPC: | G06F13/12 | [1995/01] | CPC: |
G06F13/385 (EP,US)
| Designated contracting states | AT, BE, CH, DE, DK, ES, FR, GB, GR, IE, IT, LI, LU, NL, PT, SE [1995/01] | Title | German: | Prozessorschaltung mit einem ersten Prozessor und System mit der Prozessorschaltung und einem zweiten Prozessor | [1995/01] | English: | Processor circuit comprising a first processor, and system comprising the processor circuit and a second processor | [1995/01] | French: | Circuit processeur comprenant un premier processeur, et système comprenant le circuit processeur et un deuxième processeur | [1995/01] | Examination procedure | 06.06.1995 | Examination requested [1995/31] | 22.06.1998 | Despatch of a communication from the examining division (Time limit: M06) | 22.12.1998 | Reply to a communication from the examining division | 04.03.1999 | Despatch of communication of intention to grant (Approval: No) | 14.06.1999 | Despatch of communication of intention to grant (Approval: later approval) | 02.07.1999 | Communication of intention to grant the patent | 29.09.1999 | Fee for grant paid | 29.09.1999 | Fee for publishing/printing paid | Opposition(s) | 27.02.2001 | No opposition filed within time limit [2001/20] | Fees paid | Renewal fee | 17.05.1996 | Renewal fee patent year 03 | 21.05.1997 | Renewal fee patent year 04 | 19.05.1998 | Renewal fee patent year 05 | 21.05.1999 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [Y]EP0410314 (ALLEN BRADLEY CO [US]) [Y] 1,5 * page 2, line 46 - page 3, line 20 * * page 6, line 6 - page 8, line 2 * * figures 4,5 *; | [Y]WO9222034 (UNIV PENNSYLVANIA [US]) [Y] 1,5 * page 14, line 13 - page 15, line 26 * * figure 4 *; | [A]EP0525985 (DIGITAL EQUIPMENT CORP [US]) [A] 1-8 * column 5, line 31 - column 7, line 13 ** figures 1,2 * | [A] - S. NAQVI, "Low-cost, dual-port RAM design delivers high performance", ELECTRICAL DESIGN NEWS, BOSTON, US, (19850124), no. 2, pages 155 - 160 [A] 1-8 * section: "Dual-port architecture" *; page 155 - page 157 * |