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EP About this file: EP0649083

EP0649083 - A microcontrol unit for a superpipelined, superscalar microprocessor [Right-click to bookmark this link]
Status	No opposition filed within time limit Status updated on 18.05.2001 Database last updated on 03.09.2024
Most recent event Tooltip	28.12.2007	Lapse of the patent in a contracting state New state(s): IT	published on 30.01.2008 [2008/05]
Applicant(s)	For all designated states NATIONAL SEMICONDUCTOR CORPORATION 2900 Semiconductor Drive, M.S. 16-135 Santa Clara California 95052 / US
	[N/P]
Former [2000/40]	For all designated states NATIONAL SEMICONDUCTOR CORPORATION 2900 Semiconductor Drive, M.S. 16-135 Santa Clara, California 95052 / US
Former [2000/25]	For all designated states NATIONAL SEMICONDUCTOR CORPORATION 2703 North Central Expressway Richardson, Texas / US
Former [2000/10]	For all designated states National Semiconductor Corporation 2900 Semiconductor Drive, M/S D3-579 Santa Clara, CA 95052 / US
Former [1995/16]	For all designated states CYRIX CORPORATION 2703 N. Central Expressway Richardson, Texas 75080 / US
Inventor(s)	01 / Bluhm, Mark 4545 Staten Island Plano, Texas 75082 / US
	02 / Hervin, Mark W. 17601 Preston Road, no.156 Dallas, Texas 75252 / US
	03 / McMahan, Steven C. 3311 Wyndemere Drive Richardson, Texas 75082 / US
	04 / Garibay, Raul A. Jr. 6818 Charlmont Circle Dallas Texas 75248 / US
	05 / Eitrheim, John K. 3700 Preston Road, no.1127 Plano, Texas 75093 / US
	06 / McMahon, Ronald S. 3700 Preston Road, no.1614 Plano, Texas 75093 / US
	[1995/18]
Former [1995/16]	01 / Bluhm, Mark 4545 Staten Island Plano, Texas 75082 / US
	02 / Hervin, Mark W. 17601 Preston Road, no.156 Dallas, Texas 75252 / US
	03 / McMahan, Steven C. 3311 Wyndemere Drive Richardson, Texas 75082 / US
	04 / Garibay, Raul A. Jr. 333 Melrose no. 3B Richardson, Texas 75080 / US
	05 / Eitrheim, John K. 3700 Preston Road, no.1127 Plano, Texas 75093 / US
	06 / McMahon, Ronald S. 3700 Preston Road, no.1614 Plano, Texas 75093 / US
Representative(s)	Harris, Ian Richard, et al D Young & Co LLP 120 Holborn London EC1N 2DY / GB
	[N/P]
Former [1995/16]	Harris, Ian Richard, et al c/o D. Young & Co., 21 New Fetter Lane London EC4A 1DA / GB
Application number, filing date	94307581.2	17.10.1994
	[1995/16]
Priority number, date	US19930138855	18.10.1993 Original published format: US 138855
	US19930138320	18.10.1993 Original published format: US 138320
	US19930138660	18.10.1993 Original published format: US 138660
	[1995/16]
Filing language	EN
Procedural language	EN
Publication	Type:	A2 Application without search report
	No.:	EP0649083
	Date:	19.04.1995
	Language:	EN
	[1995/16]
	Type:	A3 Search report
	No.:	EP0649083
	Date:	10.05.1995
	Language:	EN
	[1995/19]
	Type:	B1 Patent specification
	No.:	EP0649083
	Date:	19.07.2000
	Language:	EN
	[2000/29]
Search report(s)	(Supplementary) European search report - dispatched on:	EP	23.03.1995
Classification	IPC:	G06F9/38, G06F9/26, G11C7/00	[1995/18]
	CPC:	G06F9/30167 (EP,US); G06F9/261 (EP,US); G06F9/265 (EP,US); G06F9/28 (EP,US); G06F9/30145 (EP,US)
	Former IPC [1995/16]	G06F9/38, G06F9/28, G06F9/26
Designated contracting states	CH, DE, ES, FR, GB, IE, IT, LI, NL [1995/16]
Title	German:	Mikrosteuereinheit für einen superpipeline-superskalaren Mikroprozessor	[1999/32]
	English:	A microcontrol unit for a superpipelined, superscalar microprocessor	[1995/16]
	French:	Microcontrôleur pour microprocesseur superpipeline et superscalaire	[1995/16]
	Former [1995/16]	Mikrokontrolleinheit für Superpipeline-superskalaren Mikroprozessor
Examination procedure	04.10.1995	Examination requested [1995/48]
	09.04.1998	Despatch of a communication from the examining division (Time limit: M06)
	08.10.1998	Reply to a communication from the examining division
	29.06.1999	Despatch of communication of intention to grant (Approval: Yes)
	28.12.1999	Communication of intention to grant the patent
	01.03.2000	Fee for grant paid
	01.03.2000	Fee for publishing/printing paid
Opposition(s)	20.04.2001	No opposition filed within time limit [2001/27]
Fees paid	Renewal fee
	14.10.1996	Renewal fee patent year 03
	13.10.1997	Renewal fee patent year 04
	08.10.1998	Renewal fee patent year 05
	15.10.1999	Renewal fee patent year 06
Opt-out from the exclusive Tooltip competence of the Unified Patent Court	See the Register of the Unified Patent Court for opt-out data
	Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition Tooltip	CH	19.07.2000
	ES	19.07.2000
	FR	19.07.2000
	IT	19.07.2000
	LI	19.07.2000
	[2008/05]
Former [2006/14]	CH	19.07.2000
	ES	19.07.2000
	FR	19.07.2000
	LI	19.07.2000
Former [2002/26]	CH	19.07.2000
	ES	19.07.2000
	LI	19.07.2000
	FR	15.12.2000
Former [2002/02]	CH	19.07.2000
	LI	19.07.2000
	FR	15.12.2000
Former [2001/24]	FR	15.12.2000
Documents cited:	Search	[A]GB2112973 (DATA GENERAL CORP) [A] 1-3,5 * pages 28-29, sections A. and B. *;
		[A]US4430706 (SAND DUANE B [US]) [A] 11,13* the whole document *;
		[A]EP0199134 (IBM [US]) [A] 9,10 * the whole document *;
		[A]EP0223150 (HITACHI LTD [JP]) [A] 1,2,5 * the whole document *;
		[Y]EP0279953 (TEXAS INSTRUMENTS INC [US]) [Y] 1,2,5,6 * the whole document *;
		[X]EP0338564 (FUJITSU LTD [JP]) [X] 11,12 * the whole document *;
		[A]EP0372190 (COMMODORE BUSINESS MACH [US]) [A] 1,2,5 * the whole document *;
		[A]GB2230116 (INTEL CORP [US]) [A] 1,2,5 * the whole document *;
		[Y]US4984151 (DUJARI VINEET [US]) [Y] 13 * column 4, line 41 - column 5, line 19 ; column 7, lines 41-65 *;
		[X]EP0500151 (NEC CORP [JP]) [X] 11-13 * the whole document *;
		[Y] - JELEMENSKY ET AL., "The MC68332 microcontroller", IEEE MICRO, NEW YORK US, (198908), vol. 9, no. 4, pages 31 - 50 [Y] 1,2,5,6 * page 38, left column, line 24 - right column, line 39 *
		[A] - CHAPPELL ET AL., "A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture", IEEE JOURNAL OF SOLID-STATE CIRCUITS, NEW YORK US, (199111), vol. 26, no. 11, doi:doi:10.1109/4.98975, pages 1577 - 1585, XP000266666 [A] 9,10 * sections IV, V; figure 2 * DOI: http://dx.doi.org/10.1109/4.98975
		[A] - SCHMITT-LANDSIEDEL ET AL., "Pipeline architecture for fast CMOS buffer RAM's", IEEE JOURNAL OF SOLID-STATE CIRCUITS, NEW YORK US, (199006), vol. 25, no. 3, doi:doi:10.1109/4.102669, pages 741 - 746, XP000140206 [A] 9,10 * page 742, section III; figure 3 * DOI: http://dx.doi.org/10.1109/4.102669
		[XY] - CATTHOOR ET AL., "Architectural strategies for an application-specific synchronous multiprocessor environment", IEEE ACOUSTICS, SPEECH, AND SIGNAL PROCESSING MAGAZINE, NEW YORK US, (198802), vol. 36, no. 2, doi:doi:10.1109/29.1518, pages 265 - 283, XP000098757 [X] 11 * section IVa ; figures 13-15 * [Y] 13 DOI: http://dx.doi.org/10.1109/29.1518

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