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EP0690569
European procedure
Extract from the Register of European Patents
EP About this file: EP0690569
| EP0690569 - High speed synchronous logic data latch apparatus [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 27.12.2002 Database last updated on 06.07.2024 | Most recent event Tooltip | 27.12.2002 | No opposition filed within time limit | published on 05.02.2003 [2003/06] | Applicant(s) | For all designated states NEC Corporation 7-1, Shiba 5-chome Minato-ku Tokyo 108-8001 / JP | [N/P] |
| Former [2002/07] | For all designated states NEC CORPORATION 7-1, Shiba 5-chome, Minato-ku Tokyo / JP | ||
| Former [1996/01] | For all designated states NEC CORPORATION 7-1, Shiba 5-chome Minato-ku Tokyo / JP | Inventor(s) | 01 /
Obara, Takashi c/o NEC Corporation, 7-1, Shiba 5-chome Minato-ku, Tokyo / JP | [1996/01] | Representative(s) | Glawe, Delfs, Moll Partnerschaft mbB von Patent- und Rechtsanwälten Postfach 26 01 62 80058 München / DE | [N/P] |
| Former [1996/01] | Glawe, Delfs, Moll & Partner Patentanwälte Postfach 26 01 62 D-80058 München / DE | Application number, filing date | 95109948.0 | 26.06.1995 | [1996/01] | Priority number, date | JP19940165813 | 27.06.1994 Original published format: JP 16581394 | [1996/01] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0690569 | Date: | 03.01.1996 | Language: | EN | [1996/01] | Type: | A3 Search report | No.: | EP0690569 | Date: | 21.08.1996 | [1996/34] | Type: | B1 Patent specification | No.: | EP0690569 | Date: | 13.02.2002 | Language: | EN | [2002/07] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 04.07.1996 | Classification | IPC: | H03K3/012 | [1996/01] | CPC: |
H03K3/037 (EP,US);
G11C11/407 (KR);
H03K3/012 (EP,US)
| Designated contracting states | DE, FR, GB, IT [1996/01] | Title | German: | Schnelles synchrones Verriegelungsgerät für logische Daten | [1996/01] | English: | High speed synchronous logic data latch apparatus | [1996/01] | French: | Appareil rapide synchrone de verrouillage pour données logiques | [1996/01] | Examination procedure | 11.07.1996 | Examination requested [1996/37] | 13.10.2000 | Despatch of a communication from the examining division (Time limit: M06) | 18.04.2001 | Reply to a communication from the examining division | 29.05.2001 | Despatch of communication of intention to grant (Approval: Yes) | 07.08.2001 | Communication of intention to grant the patent | 08.10.2001 | Fee for grant paid | 08.10.2001 | Fee for publishing/printing paid | Opposition(s) | 14.11.2002 | No opposition filed within time limit [2003/06] | Fees paid | Renewal fee | 20.06.1997 | Renewal fee patent year 03 | 23.06.1998 | Renewal fee patent year 04 | 22.06.1999 | Renewal fee patent year 05 | 19.06.2000 | Renewal fee patent year 06 | 18.06.2001 | Renewal fee patent year 07 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]US3783254 (EICHELBERGER E) [A] 8,12,16 * column 10, line 29 - column 11, line 55 * * column 13, line 12 - line 49 * * figures 7,12 *; | [X]EP0541840 (HEWLETT PACKARD GMBH [DE]) [X] 1,12 * page 6, line 39 - page 7, line 7; figure 3 *; | [A]EP0548894 (EASTMAN KODAK CO [US]) [A] 12,14,16,18 * page 4, line 57 - page 5, line 13 * * page 7, line 1 - line 12 ** figures 2,4 *; | [X]EP0552046 (SONY CORP [JP]) [X] 1,6,10 * column 4, line 15 - column 6, line 54; figures 5,8 * |