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EP0699920
European procedure
Extract from the Register of European Patents
EP About this file: EP0699920
| EP0699920 - Semiconductor integrated circuit with a testable block [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 07.02.2003 Database last updated on 31.08.2024 | Most recent event Tooltip | 17.10.2008 | Change - applicant | published on 19.11.2008 [2008/47] | Applicant(s) | For all designated states MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 1006, Oaza Kadoma Kadoma-shi Osaka 571-8501 / JP | [2008/47] |
| Former [2002/14] | For all designated states MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 1006, Oaza Kadoma Kadoma-shi, Osaka 571-0050 / JP | ||
| Former [1996/10] | For all designated states MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 1006, Oaza Kadoma Kadoma-shi, Osaka 571 / JP | Inventor(s) | 01 /
Motohara, Akira 7-4-E-604, Mukogaoka Sanda-shi, Hyogo 669-13 / JP | 02 /
Takeoka, Sadami 2-7, Minamiterakatakitadori Moriguchi-shi, Osaka 570 / JP | 03 /
Kishi, Tetsuji 1-12-711, Shoji-cho Kadoma-shi, Osaka 571 / JP | 04 /
Nakajima, Masaitsu 2-10-24-604, Seiiku Joto-ku, Osaka-shi, Osaka 536 / JP | [2001/47] |
| Former [1996/10] | 01 /
Motohara, Akira 7-4-E-604, Mukogaoka Sanda-shi, Hyogo 669-13 / JP | ||
| 02 /
Takeoka, Sadami 2-7, Minamiterakatakitadori Morilguchi-shi, Osaka 570 / JP | |||
| 03 /
Kishi, Tetsuji 1-12-711, Shoji-cho Kadoma-shi, Osaka 571 / JP | |||
| 04 /
Nakajima, Masaitsu 2-10-24-604, Seiiku Joto-ku, Osaka-shi, Osaka 536 / JP | Representative(s) | Grünecker Patent- und Rechtsanwälte PartG mbB Leopoldstrasse 4 80802 München / DE | [N/P] |
| Former [1996/10] | Grünecker, Kinkeldey, Stockmair & Schwanhäusser Anwaltssozietät Maximilianstrasse 58 D-80538 München / DE | Application number, filing date | 95113487.3 | 28.08.1995 | [1996/10] | Priority number, date | JP19940203842 | 29.08.1994 Original published format: JP 20384294 | JP19940250535 | 17.10.1994 Original published format: JP 25053594 | [1996/10] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0699920 | Date: | 06.03.1996 | Language: | EN | [1996/10] | Type: | A3 Search report | No.: | EP0699920 | Date: | 10.09.1997 | [1997/37] | Type: | B1 Patent specification | No.: | EP0699920 | Date: | 03.04.2002 | Language: | EN | [2002/14] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 23.07.1997 | Classification | IPC: | G01R31/28, G06F11/267, G01R31/3185 | [1997/35] | CPC: |
G01R31/318536 (EP);
H01L22/00 (KR)
|
| Former IPC [1996/10] | G01R31/28, G06F11/267 | Designated contracting states | DE, FR, GB, NL [1996/10] | Title | German: | Integrierte Halbleiterschaltung mit prüfbaren Blöcken | [2001/25] | English: | Semiconductor integrated circuit with a testable block | [1996/10] | French: | Circuit integré à semi-conducteur à bloc testable | [1996/10] |
| Former [1996/10] | Halbleiter-integrierte Schaltung mit prüfbaren Blöcken | Examination procedure | 28.11.1997 | Amendment by applicant (claims and/or description) | 28.11.1997 | Examination requested [1998/05] | 25.05.2000 | Despatch of a communication from the examining division (Time limit: M04) | 02.10.2000 | Reply to a communication from the examining division | 06.06.2001 | Despatch of communication of intention to grant (Approval: Yes) | 05.10.2001 | Communication of intention to grant the patent | 21.12.2001 | Fee for grant paid | 21.12.2001 | Fee for publishing/printing paid | Opposition(s) | 06.01.2003 | No opposition filed within time limit [2003/13] | Fees paid | Renewal fee | 29.08.1997 | Renewal fee patent year 03 | 26.08.1998 | Renewal fee patent year 04 | 26.08.1999 | Renewal fee patent year 05 | 30.08.2000 | Renewal fee patent year 06 | 30.08.2001 | Renewal fee patent year 07 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | NL | 03.04.2002 | [2003/08] | Documents cited: | Search | [A]US4779273 (BEUCLER FREDERICK P [US], et al) [A] 1-7 * abstract *; | [A]US3806891 (EICHELBERGER E, et al) [A] 1-7 * abstract *; | [A]EP0188076 (PLESSEY OVERSEAS [GB]) [A] 1-7 * abstract *; | [A]DE9005697U (SIEMENS AG.) [A] 2,3 * figures 1,2; claim 1 *; | [A] - BEAUSANG J. ET AL., "Incorporation of the BILBO technique witihin an existing chip design", PROCEEDINGS OF THE IEEE 1985 CUSTOM INTEGRATED CIRCUITS CONFERENCE, PORTLAND, OREGON, US, (19850520), pages 328 - 331, XP002034085 [A] 1-7 * page 330; figure 3 * |