blank Quick help
blank Maintenance news

Scheduled maintenance

Regular maintenance outages:
between 05.00 and 05.15 hrs CET (Monday to Sunday).

Other outages
Availability
Register Forum

2022.02.11

More...
blank News flashes

News Flashes

New version of the European Patent Register – SPC proceedings information in the Unitary Patent Register.

2024-07-24

More...
blank Related links

Release notes
European Patent Register Assistant
European Patent Register Resource Book
European Patent Register – pocket guide
FAQ - European Patent Register
FAQ - Register Alert
Federated Register (Flyer)
Global Dossier (Flyer)
Register events
Deep link coverage
Federated Register content
The Patent Information Tour
Fair use charter

Extract from the Register of European Patents

EP About this file: EP0714119

EP0714119 - Pattern forming process and process for preparing semiconductor device utilizing said pattern forming process [Right-click to bookmark this link]
Former [1996/22]Pattern forming process, apparatus for forming said pattern and process for preparing semiconductor device utilizing said pattern forming process
[2001/40]
StatusNo opposition filed within time limit
Status updated on  10.10.2003
Database last updated on 24.08.2024
Most recent event   Tooltip04.01.2008Lapse of the patent in a contracting state
New state(s): IT		published on 06.02.2008  [2008/06]
Applicant(s)For all designated states
CANON KABUSHIKI KAISHA
30-2, 3-chome, Shimomaruko, Ohta-ku
Tokyo / JP
[N/P]
Former [1996/22]For all designated states
CANON KABUSHIKI KAISHA
30-2, 3-chome, Shimomaruko, Ohta-ku
Tokyo / JP
Inventor(s)01 / Yagi, Takayuki
c/o Canon K.K., 30-2, 3-chome, Shimomaruko
Ohta-ku, Tokyo / JP
02 / Komatsu, Toshiyuki
c/o Canon K.K., 30-2, 3-chome, Shimomaruko
Ohta-ku, Tokyo / JP
03 / Sato, Yasue
c/o Canon K.K., 30-2, 3-chome, Shimomaruko
Ohta-ku, Tokyo / JP
04 / Kawate, Shinichi
c/o Canon K.K., 30-2, 3-chome, Shimomaruko
Ohta-ku, Tokyo / JP
[1996/22]
Representative(s)Beresford, Keith Denis Lewis, et al
Beresford Crump LLP
16 High Holborn
London WC1V 6BX / GB
[N/P]
Former [1996/22]Beresford, Keith Denis Lewis, et al
BERESFORD & Co. 2-5 Warwick Court High Holborn
London WC1R 5DJ / GB
Application number, filing date95203233.208.05.1991
[1996/22]
Priority number, dateJP1990011764409.05.1990         Original published format: JP 11764490
JP1990011867510.05.1990         Original published format: JP 11867590
JP1990015868719.06.1990         Original published format: JP 15868790
JP1990017444303.07.1990         Original published format: JP 17444390
JP1990030855016.11.1990         Original published format: JP 30855090
[1996/22]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0714119
Date:29.05.1996
Language:EN
[1996/22]
Type: A3 Search report 
No.:EP0714119
Date:03.07.1996
[1996/27]
Type: B1 Patent specification 
No.:EP0714119
Date:04.12.2002
Language:EN
[2002/49]
Search report(s)(Supplementary) European search report - dispatched on:EP14.05.1996
ClassificationIPC:H01L21/033, H01L21/308, H01L21/321, G03F7/16
[1996/23]
CPC:
H01L21/32139 (EP,US); G03F7/16 (EP,US); G03F7/167 (EP,US);
G03F7/2043 (EP,US); H01L21/3081 (EP,US); H01L21/31144 (EP,US);
Y10S438/908 (EP,US) (-)
Former IPC [1996/22]H01L21/027, G03F7/00
Designated contracting statesAT,   BE,   CH,   DE,   DK,   ES,   FR,   GB,   GR,   IT,   LI,   LU,   NL,   SE [1996/22]
TitleGerman:Verfahren zur Erzeugung einer Struktur und Verfahren zum Vorbereiten einer halbleitenden Anordnung mit Hilfe dieses Verfahrens[2001/40]
English:Pattern forming process and process for preparing semiconductor device utilizing said pattern forming process[2001/40]
French:Procédé pour former un motif et procédé de préparation d'un composant semi-conducteur utilisant ledit procédé[2001/40]
Former [1996/22]Verfahren und Einrichtung zur Erzeugung einer Struktur und Verfahren zum Vorbereiten einer halbleitenden Anordnung mit Hilfe dieses Verfahrens
Former [1996/22]Pattern forming process, apparatus for forming said pattern and process for preparing semiconductor device utilizing said pattern forming process
Former [1996/22]Procédé et appareillage pour former un motif et procédé de préparation d'un composant semi-conducteur utilisant ledit procédé
Examination procedure13.11.1996Examination requested  [1997/02]
03.10.1997Despatch of a communication from the examining division (Time limit: M06)
13.05.1998Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time
21.07.1998Reply to a communication from the examining division
08.11.1999Despatch of a communication from the examining division (Time limit: M06)
11.05.2000Reply to a communication from the examining division
25.09.2001Despatch of communication of intention to grant (Approval: Yes)
07.05.2002Communication of intention to grant the patent
19.07.2002Fee for grant paid
19.07.2002Fee for publishing/printing paid
Parent application(s)   TooltipEP91304134.9  / EP0456479
Opposition(s)05.09.2003No opposition filed within time limit [2003/48]
Request for further processing for:21.07.1998Request for further processing filed
21.07.1998Full payment received (date of receipt of payment)
Request granted
18.08.1998Decision despatched
Fees paidRenewal fee
18.12.1995Renewal fee patent year 03
18.12.1995Renewal fee patent year 04
18.12.1995Renewal fee patent year 05
22.05.1996Renewal fee patent year 06
21.05.1997Renewal fee patent year 07
20.05.1998Renewal fee patent year 08
19.05.1999Renewal fee patent year 09
22.05.2000Renewal fee patent year 10
25.05.2001Renewal fee patent year 11
27.05.2002Renewal fee patent year 12
Opt-out from the exclusive  Tooltip
competence of the Unified
Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipAT04.12.2002
BE04.12.2002
CH04.12.2002
FR04.12.2002
GR04.12.2002
IT04.12.2002
LI04.12.2002
NL04.12.2002
DK04.03.2003
SE04.03.2003
DE05.03.2003
LU08.05.2003
ES27.06.2003
[2008/06]
Former [2006/14]AT04.12.2002
BE04.12.2002
CH04.12.2002
FR04.12.2002
GR04.12.2002
LI04.12.2002
NL04.12.2002
DK04.03.2003
SE04.03.2003
DE05.03.2003
LU08.05.2003
ES27.06.2003
Former [2004/39]AT04.12.2002
BE04.12.2002
CH04.12.2002
GR04.12.2002
LI04.12.2002
NL04.12.2002
DK04.03.2003
SE04.03.2003
DE05.03.2003
LU08.05.2003
ES27.06.2003
Former [2004/04]AT04.12.2002
BE04.12.2002
CH04.12.2002
GR04.12.2002
LI04.12.2002
NL04.12.2002
DK04.03.2003
SE04.03.2003
DE05.03.2003
ES27.06.2003
Former [2004/02]AT04.12.2002
BE04.12.2002
CH04.12.2002
GR04.12.2002
LI04.12.2002
NL04.12.2002
DK04.03.2003
SE04.03.2003
DE05.03.2003
Former [2003/51]AT04.12.2002
BE04.12.2002
CH04.12.2002
GR04.12.2002
LI04.12.2002
NL04.12.2002
SE04.03.2003
Former [2003/39]AT04.12.2002
CH04.12.2002
GR04.12.2002
LI04.12.2002
NL04.12.2002
SE04.03.2003
Former [2003/37]AT04.12.2002
GR04.12.2002
NL04.12.2002
SE04.03.2003
Former [2003/31]GR04.12.2002
NL04.12.2002
SE04.03.2003
Former [2003/30]NL04.12.2002
SE04.03.2003
Former [2003/27]SE04.03.2003
Documents cited:Search[A]FR2077574  (GEN ELECTRIC) [A] 1-3,5,6,13 * example 6 *;
 [A]US4348473  (OKUMURA KOJI, et al) [A] 2* claim 1 *;
 [A]EP0204538  (TOSHIBA KK [JP]) [A] 1,2,4,7-13 * figures 6,7 *;
 [Y]US4698238  (HAYASAKA NOBUO [JP], et al) [Y] 1,2,4-13,18,19 * example 1 *;
 [Y]WO8907285  (MASSACHUSETTS INST TECHNOLOGY [US]) [Y] 1-6,8-13,15-18 * the whole document *;
 [Y]  - ANTHONY ET AL, "In situ cleaning of silicon substrate surfaces by remote plasma-excited hydrogen", JOURNAL OF VACUUM SCIENCE AND TECHNOLOGY: PART B, NEW YORK US, vol. 7, no. 4, pages 621 - 626, XP000168951 [Y] 1-13,15-18 * abstract * * page 623, column L, paragraph 2 *

DOI:   http://dx.doi.org/10.1116/1.584805
 [Y]  - TANEYA ET AL, "Photo-oxidation of GaAs for in situ patterned-mask formation prior to chlorine gas etching", APPLIED PHYSICS LETTERS, NEW YORK US, (19900101), vol. 56, no. 1, pages 98 - 100, XP000126795 [Y] 19 * figure 1 *

DOI:   http://dx.doi.org/10.1063/1.102616
 [A]  - TAKAKUWA ET AL, "Low-temperature cleaning of HF passivated Si(111) surface with VUV light", JAPANESE JOURNAL OF APPLIED PHYSICS, TOKYO JP, vol. 28, no. 7, pages L1274 - L1277, XP000073560 [A] 1 * abstract *

DOI:   http://dx.doi.org/10.1143/JJAP.28.L1274
 [A]  - "Antireflective Chrome photomasks", IBM TECHNICAL DISCLOSURE BULLETIN, NEW YORK US, vol. 13, no. 3, page 752 [A] 14 * the whole document *
by applicantJPS62219525
    - NIKKEI MICRODEVICE, (198610), vol. 2 EXTRA
    - BRANCH OF SOCIETY OF APPLIED ELECTRONIC PHYSICAL PROPERTIES, page 13
    - SEMI TECHNOL. SYMP., (1985), page F-3-1
    - SEKINE, OKANO, HORIIKE, THE FIFTH DRY PROCESS SYMPOSIUM LECTURE PRETEXT, (1983), page 97
    - J. VAC. SCI. TECHNOL., (1985), vol. B3, no. 5, page 1507
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.