blank Quick help
blank Maintenance news

Scheduled maintenance

Regular maintenance outages:
between 05.00 and 05.15 hrs CET (Monday to Sunday).

Other outages
Availability
Register Forum

2022.02.11

More...
blank News flashes

News Flashes

New version of the European Patent Register – SPC proceedings information in the Unitary Patent Register.

2024-07-24

More...
blank Related links

Extract from the Register of European Patents

EP About this file: EP0678914

EP0678914 - Method for planarizing an integrated circuit topography [Right-click to bookmark this link]
StatusThe application is deemed to be withdrawn
Status updated on  13.08.1999
Database last updated on 24.08.2024
Most recent event   Tooltip01.08.2008Change - applicantpublished on 03.09.2008  [2008/36]
Applicant(s)For all designated states
ADVANCED MICRO DEVICES, INC.
One AMD Place Mail Stop 68 P.O. Box 3453
Sunnyvale CA 94088-3453 / US
[2008/36]
Former [1995/43]For all designated states
ADVANCED MICRO DEVICES INC.
One AMD Place, P.O. Box 3453
Sunnyvale, California 94088-3453 / US
Inventor(s)01 / Dawson, Robert
3504 Beartree Cir
Austin, Texas 78730 / US
[1995/43]
Representative(s)Wright, Hugh Ronald, et al
Brookes Batchellor LLP
1 Boyne Park
Tunbridge Wells Kent TN4 8EL / GB
[N/P]
Former [1995/43]Wright, Hugh Ronald, et al
Brookes & Martin 52/54 High Holborn
London WC1V 6SE / GB
Application number, filing date95301415.606.03.1995
[1995/43]
Priority number, dateUS1994022917018.04.1994         Original published format: US 229170
[1995/43]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0678914
Date:25.10.1995
Language:EN
[1995/43]
Type: A3 Search report 
No.:EP0678914
Date:19.02.1997
[1997/08]
Search report(s)(Supplementary) European search report - dispatched on:EP07.01.1997
ClassificationIPC:H01L21/768, H01L21/3105
[1995/43]
CPC:
H01L21/31051 (EP,US); H01L21/76819 (EP,US)
Designated contracting statesAT,   BE,   DE,   DK,   ES,   FR,   GB,   GR,   IE,   IT,   LU,   NL,   PT,   SE [1995/43]
TitleGerman:Verfahren zur Planarizierung einer integrierten Schaltung[1995/43]
English:Method for planarizing an integrated circuit topography[1995/43]
French:Procédé de planarization d'un circuit intégré[1995/43]
Examination procedure23.07.1997Examination requested  [1997/39]
03.10.1997Despatch of a communication from the examining division (Time limit: M04)
29.01.1998Reply to a communication from the examining division
12.01.1999Despatch of a communication from the examining division (Time limit: M02)
23.03.1999Application deemed to be withdrawn, date of legal effect  [1999/39]
29.04.1999Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time  [1999/39]
Fees paidRenewal fee
19.03.1997Renewal fee patent year 03
05.03.1998Renewal fee patent year 04
04.03.1999Renewal fee patent year 05
Opt-out from the exclusive  Tooltip
competence of the Unified
Patent Court
See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:Search[X]JPH05235184  (NEC CORP) [X] 9,10,14-17,19;
 US5332694  [ ] (SUZUKI MIEKO [JP]) [ ] * column 3, line 64 - column 4, line 59; figures 2,5 *;
 [X]DE4135810  (MITSUBISHI ELECTRIC CORP [JP]) [X] 1,3,5,6,8-10,14,16,17,19 * page 4, line 60 - page 5, line 7; claim - *;
 [E]WO9429899  (VLSI TECHNOLOGY INC [US]) [E] 1,3,6,9,10,14,17,19 * abstract *;
 [A]US5252515  (TSAI LIH-SHYNG [TW], et al) [A] 1-8 * column A; figure 2 *;
 [A]WO9109422  (MITEL CORP [CA]) [A] 1-19 * claims 1-4,17 *;
 [A]US5266525  (MOROZUMI YUKIO [JP]) [A] 9-19 * column 5, line 1 - line 61 *;
 [A]US4721548  (MORIMOTO SEIICHI [US]) [A] 11,12 * column A *
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.