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EP0698848
European procedure
Extract from the Register of European Patents
EP About this file: EP0698848
| EP0698848 - Method and apparatus for testing an integrated circuit [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 08.09.2000 Database last updated on 22.08.2024 | Most recent event Tooltip | 08.09.2000 | No opposition filed within time limit | published on 25.10.2000 [2000/43] | Applicant(s) | For all designated states STMicroelectronics Limited 1000 Aztec West, Almondsbury Bristol BS12 4SQ / GB | [N/P] |
| Former [1999/08] | For all designated states STMicroelectronics Limited 1000 Aztec West, Almondsbury Bristol BS12 4SQ / GB | ||
| Former [1996/09] | For all designated states SGS-THOMSON MICROELECTRONICS LTD. 1000 Aztec West, Almondsbury Bristol BS12 4SQ / GB | Inventor(s) | 01 /
Beat, Robert 1B Westfield Place Clifton, Bristol BS8 4AY / GB | [1996/09] | Representative(s) | Driver, Virginia Rozanne, et al Page White & Farrer Limited Bedford House 21A John Street London WC1N 2BF / GB | [N/P] |
| Former [1996/09] | Driver, Virginia Rozanne, et al Page White & Farrer 54 Doughty Street London WC1N 2LS / GB | Application number, filing date | 95305818.7 | 21.08.1995 | [1996/09] | Priority number, date | GB19940017297 | 26.08.1994 Original published format: GB 9417297 | [1996/09] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0698848 | Date: | 28.02.1996 | [1996/09] | Type: | B1 Patent specification | No.: | EP0698848 | Date: | 10.11.1999 | Language: | EN | [1999/45] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 27.10.1995 | Classification | IPC: | G06F11/26, G11C29/00 | [1996/09] | CPC: |
G06F11/27 (EP,US)
| Designated contracting states | DE, FR, GB, IT [1996/09] | Title | German: | Verfahren und Gerät zur Prüfung integrierter Schaltungen | [1996/09] | English: | Method and apparatus for testing an integrated circuit | [1996/09] | French: | Procédé et appareil de test de circuit intégré | [1996/09] | Examination procedure | 17.04.1996 | Examination requested [1996/24] | 02.07.1997 | Despatch of a communication from the examining division (Time limit: M04) | 20.10.1997 | Reply to a communication from the examining division | 26.03.1998 | Despatch of a communication from the examining division (Time limit: M04) | 04.08.1998 | Reply to a communication from the examining division | 29.09.1998 | Despatch of communication of intention to grant (Approval: Yes) | 19.02.1999 | Communication of intention to grant the patent | 07.05.1999 | Fee for grant paid | 07.05.1999 | Fee for publishing/printing paid | Opposition(s) | 11.08.2000 | No opposition filed within time limit [2000/43] | Fees paid | Renewal fee | 28.08.1997 | Renewal fee patent year 03 | 25.08.1998 | Renewal fee patent year 04 | 27.08.1999 | Renewal fee patent year 05 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X]US4167780 (HAYASHI HIROMU) [X] 1-9,14 * the whole document *; | [A]US4575792 (KEELEY JAMES W [US]) [A] 1,12 * abstract * * column 18, line 39 - column 28, line 61 *; | [A]US4912395 (SATO YOSHIO [JP], et al) [A] 1,12 * column 1, line 44 - column 3, line 32; figure 1 *; | [A]US3343141 (HACKL FRANK J) [A] 1,2,4-7,12 * abstract * * column 1, line 45 - column 2, line 22 * * column 3, line 27 - column 4, line 30 * * column 4, line 66 - column 10, line 50 * * column 10, line 53 - line 64; figures 1-3 * * column 13, line 19 - column 14, line 6; figures 1-3; claims 1-14 *; | [A]US4481627 (BEAUCHESNE ROBERT C [US], et al) [A] 1,12 * the whole document *; | [A]US3961254 (CAVALIERE JOSEPH R, et al) [A] 1,12 * the whole document *; | [A]US3961251 (HURLEY WILLIAM J, et al) [A] 1,12 * column W *; | [X]US3519808 (LAWDER ROBERT ERNEST) [X] 1,14 * column 1, line 15 - column 8, line 66; figures 1-3 * |