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EP0718880
European procedure
Extract from the Register of European Patents
EP About this file: EP0718880
| EP0718880 - Apparatus and method for estimating chip yield [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 18.01.2002 Database last updated on 13.09.2024 | Most recent event Tooltip | 11.07.2008 | Change - representative | published on 13.08.2008 [2008/33] | Applicant(s) | For all designated states TEXAS INSTRUMENTS INC. 13500 North Central Expressway Dallas Texas 75243 / US | [N/P] |
| Former [1996/26] | For all designated states TEXAS INSTRUMENTS INC. 13500 North Central Expressway Dallas, Texas 75243 / US | Inventor(s) | 01 /
Kamatsuzaki, Takao 106 Ishikawa Ishioka-shi Ibaraki-ken / JP | 02 /
Miyai, Yoichi 1-6-C303 Nishi Toride-shi Ibaraki-ken / JP | 03 /
Fukuhara, Hideyuki 520-105 Ami-Machi Inashiki-gun Ibaraki-ken / JP | [1996/26] | Representative(s) | Holt, Michael Texas Instruments Limited European Patent Department 3rd Floor 401 Grafton Gate Milton Keynes MK9 1AQ / GB | [N/P] |
| Former [2008/33] | Holt, Michael Texas Instruments Limited European Patents Department 800 Pavilion Drive Northampton NN4 7YL / GB | ||
| Former [1996/26] | Holt, Michael Texas Instruments Limited, Kempton Point, 68 Staines Road West Sunbury-on-Thames, Middlesex TW16 7AX / GB | Application number, filing date | 95308971.1 | 11.12.1995 | [1996/26] | Priority number, date | JP19940306035 | 09.12.1994 Original published format: JP 30603594 | [1999/17] |
| Former [1996/26] | JP19940306033 | 09.12.1994 | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0718880 | Date: | 26.06.1996 | Language: | EN | [1996/26] | Type: | A3 Search report | No.: | EP0718880 | Date: | 05.02.1997 | [1997/06] | Type: | B1 Patent specification | No.: | EP0718880 | Date: | 14.03.2001 | Language: | EN | [2001/11] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 19.12.1996 | Classification | IPC: | H01L21/66 | [1996/26] | CPC: |
H01L22/20 (EP,US);
H01L22/00 (KR);
H01L2924/0002 (EP,US)
| C-Set: |
H01L2924/0002, H01L2924/00 (EP,US)
| Designated contracting states | DE, FR, GB, IT, NL [1996/26] | Title | German: | Apparat und Methode zur Chipausbeuteermittlung | [1999/44] | English: | Apparatus and method for estimating chip yield | [1996/26] | French: | Appareil et méthode d'estimation de rendement de puces | [1996/26] |
| Former [1996/26] | Apparat und Methode zur Ausbeuteermittlung | Examination procedure | 05.08.1997 | Examination requested [1997/40] | 18.10.1999 | Despatch of communication of intention to grant (Approval: Yes) | 31.07.2000 | Communication of intention to grant the patent | 10.11.2000 | Fee for grant paid | 10.11.2000 | Fee for publishing/printing paid | Opposition(s) | 15.12.2001 | No opposition filed within time limit [2002/10] | Fees paid | Renewal fee | 02.01.1998 | Renewal fee patent year 03 | 04.01.1999 | Renewal fee patent year 04 | 05.01.2000 | Renewal fee patent year 05 | 02.01.2001 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [DA]JPS4840376 (APPLICANT UNKNOWN) [DA] 1-3 * the whole document *; | [PA]JPH07306848 ; | [A]US3751647 (MAEDER R, et al) [A] 1-3 * claims 1,4 *; | [PX] - FUKUHARA H; KOMATSUZAKI T; BOKU K; MIYAI Y, "Use of a Monte Carlo wiring yield simulator to optimize design of random logic circuits for yield enhancement", IEICE TRANSACTIONS ON ELECTRONICS, JAPAN, (199507), vol. E87-C, no. 7, pages 852 - 857, XP002020369 [PX] 1-3 * page 853, column R, paragraph 3 - page 854, column R, paragraph 2 * | [PA] - PATENT ABSTRACTS OF JAPAN, vol. 95, no. 011, & JP07306848 A 19951121 (MATSUSHITA ELECTRON CORP) [PA] 1-3 * abstract * | [A] - JITENDRA KHARE ET AL, "SRAM-BASED EXTRACTION OF DEFECT CHARACTERISTICS", PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES (ICMTS), SAN DIEGO, MAR. 22 - 25, 1994, INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, (19940322), pages 98 - 107, XP000481297 [A] 1-3 * figures 3,5 * | [A] - HATTORI T ET AL, "AN AUTOMATED PARTICLE DETECTION AND IDENTIFICATION SYSTEM IN VLSI WAFER PROCESSING", SOLID STATE TECHNOLOGY, (19910901), vol. 34, no. 9, pages S01 - S06, XP000541403 [A] 1-3 * figure 8 * DOI: http://dx.doi.org/10.1016/0038-1101(91)90195-5 | by applicant | JPS4840376B |