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EP0741410
European procedure
Extract from the Register of European Patents
EP About this file: EP0741410
| EP0741410 - Semiconductor device and method for manufacturing the same [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 08.05.2009 Database last updated on 11.04.2026 | Most recent event Tooltip | 08.05.2009 | No opposition filed within time limit | published on 10.06.2009 [2009/24] | Applicant(s) | For all designated states Oki Electric Industry Co., Ltd. 7-12, Toranomon 1-chome Minato-ku Tokyo / JP | [2008/27] |
| Former [1996/45] | For all designated states Oki Electric Industry Co., Ltd. 7-12, Toranomon 1-chome Minato-ku Tokyo / JP | Inventor(s) | 01 /
Onoda, Hiroshi, c/o Oki Electric Ind. Co., Ltd 7-12 Toranomon 1-chome Minato-ku, Tokyo / JP | [1996/45] | Representative(s) | Read, Matthew Charles, et al Venner Shipley LLP 200 Aldersgate London EC1A 4HD / GB | [N/P] |
| Former [1996/45] | Read, Matthew Charles, et al Venner Shipley & Co. 20 Little Britain London EC1A 7DH / GB | Application number, filing date | 96106938.2 | 02.05.1996 | [1996/45] | Priority number, date | JP19950107177 | 01.05.1995 Original published format: JP 10717795 | [1996/45] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0741410 | Date: | 06.11.1996 | Language: | EN | [1996/45] | Type: | A3 Search report | No.: | EP0741410 | Date: | 04.06.1997 | [1997/23] | Type: | B1 Patent specification | No.: | EP0741410 | Date: | 02.07.2008 | Language: | EN | [2008/27] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 16.04.1997 | Classification | IPC: | H01L23/522 | [1996/45] | CPC: |
H10W20/42 (EP,KR,US)
| Designated contracting states | DE, FR, GB [1996/45] | Title | German: | Halbleiteranordnung und Verfahren zu ihrer Herstellung | [1996/45] | English: | Semiconductor device and method for manufacturing the same | [1996/45] | French: | Dispositif semi-conducteur et procédé de fabrication | [1996/45] | Examination procedure | 31.07.1997 | Examination requested [1997/40] | 03.09.1999 | Despatch of a communication from the examining division (Time limit: M04) | 25.11.1999 | Reply to a communication from the examining division | 20.03.2001 | Despatch of a communication from the examining division (Time limit: M04) | 02.07.2001 | Reply to a communication from the examining division | 08.02.2002 | Despatch of a communication from the examining division (Time limit: M04) | 08.03.2002 | Reply to a communication from the examining division | 06.11.2007 | Communication of intention to grant the patent | 17.03.2008 | Fee for grant paid | 17.03.2008 | Fee for publishing/printing paid | Opposition(s) | 03.04.2009 | No opposition filed within time limit [2009/24] | Fees paid | Renewal fee | 28.05.1998 | Renewal fee patent year 03 | 25.05.1999 | Renewal fee patent year 04 | 23.05.2000 | Renewal fee patent year 05 | 25.05.2001 | Renewal fee patent year 06 | 28.05.2002 | Renewal fee patent year 07 | 30.05.2003 | Renewal fee patent year 08 | 21.05.2004 | Renewal fee patent year 09 | 17.05.2005 | Renewal fee patent year 10 | 18.05.2006 | Renewal fee patent year 11 | 17.05.2007 | Renewal fee patent year 12 | 19.05.2008 | Renewal fee patent year 13 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [XY] EP0124181 (PHILIPS NV et al.) [X] 1,4-9,11,13,17 * page 4, line 36 - page 12, line 12; figures 1-5 *[Y] 10,12,14 | [PXA] EP0670597 (TOSHIBA KK et al.) [PX] 1,4-9,11,13,15,17 * column 5, line 36 - column 7, line 48; figures 3-9 * * column 1, line 16 - column 2, line 18; figures 1,2 *[A] 16,10,12,14 | [XA] EP0480580 (CANON KK et al.) [X] 1,3,4,7,9,11 * page 16, line 32 - page 17, line 19; figures 1A,1B,10A,10B *[A] 5,6,8,10,12-14,17 | [XA] US5233223 (MURAYAMA MOTOAKI et al.) [X] 5,6,13 * column 4, line 10 - column 5, line 40; figures 2-4 *[A] 1-4,7-12,14,17 | [XA] DE4328474 (GOLD STAR ELECTRONICS et al.) [X] 5,6 * column 4, line 19 - column 5, line 38; figures 6,7 *[A] 1-4,7-14,17 | [X] JPS5975645 | [X] EP0289274 (HEWLETT PACKARD CO et al.) [X] 15,16 * column 1, line 27 - line 32 * * column 2, line 41 - column 3, line 1 * * column 3, line 53 - column 4, line 24; figures 2,3 * | [XA] EP0513715 (SIEMENS AG et al.) [X] 15 * column 1, line 26 - column 2, line 4; figure 1 *[A] 16 | [YA] ROBERTS B ET AL: "INTERCONNECT METALLIZATION FOR FUTURE DEVICE GENERATIONS", SOLID STATE TECHNOLOGY, vol. 38, no. 2, 1 February 1995 (1995-02-01), pages 69/70, 72, 74, 76, 78, XP000490071 [Y] 10,12,14 * page 69, column L, paragraph 1 - column R, paragraph 2; figure 1 *[A] 1,5-8,11,13,17 DOI: http://dx.doi.org/10.1016/0038-1101(94)E0050-O | [XA] R.M. GEFFKEN: "Multi-level metallurgy for master image structured logic", PROCEEDINGS OF THE IEEE INTERNATIONAL ELECTRON DEVICES MEETING 83, December 1983 (1983-12-01), NEW YORK, US, pages 542 - 545, XP000195641 [X] 1,3-9,17 * page 542, column R, paragraph 3 - page 543, column L, paragraph 2; figure 2 * * page 542, column L, paragraph 3 - column R, paragraph 2; figures 1A,1B * [A] 15,16,11-14 | [XA] DIJK VAN J M F ET AL: "A TWO-LEVEL METALLIZATION SYSTEM WITH OVERSIZED VIAS AND A TI:W ETCH BARRIER", IEEE VLSI MULTILEVEL INTERCONNECTION CONFERENCE, SANTA CLARA, JUNE 25 - 26, 1985, no. 1985, 25 June 1985 (1985-06-25), INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 123 - 130, XP000010249 [X] 1,4-9,17 * the whole document * [A] 11-14 | [X] PATENT ABSTRACTS OF JAPAN vol. 008, no. 185 (E - 262) 24 August 1984 (1984-08-24) [X] 15,16 * abstract * |