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EP0738958
European procedure
Extract from the Register of European Patents
EP About this file: EP0738958
| EP0738958 - Multiplier [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 12.05.2000 Database last updated on 19.07.2024 | Most recent event Tooltip | 04.01.2008 | Lapse of the patent in a contracting state New state(s): IT | published on 06.02.2008 [2008/06] | Applicant(s) | For all designated states THOMSON multimedia 46 quai A. Le Gallo 92648 Boulogne Cédex / FR | [1999/27] |
| Former [1998/13] | For all designated states THOMSON multimedia 46, Quai A. Le Gallo 92648 Boulogne Cédex / FR | ||
| Former [1996/43] | For all designated states THOMSON multimedia 9, place des Vosges La Défense 5 92400 Courbevoie / FR | Inventor(s) | 01 /
Chan Yan Fong, Joseph 61, Domaine de 1'Ile 67400 Illkirch / FR | [1996/43] | Representative(s) | Hartnack, Wolfgang, et al Deutsche Thomson OHG Karl-Wiechert-Allee 1D 30625 Hannover / DE | [N/P] |
| Former [1996/43] | Hartnack, Wolfgang, Dipl.-Ing., et al Deutsche Thomson-Brandt GmbH Licensing & Intellectual Property, Göttinger Chaussee 76 30453 Hannover / DE | Application number, filing date | 96109443.0 | 12.10.1992 | [1996/43] | Priority number, date | EP19910402797 | 21.10.1991 Original published format: EP 91402797 | [1996/43] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0738958 | Date: | 23.10.1996 | Language: | EN | [1996/43] | Type: | A3 Search report | No.: | EP0738958 | Date: | 15.01.1997 | [1997/03] | Type: | B1 Patent specification | No.: | EP0738958 | Date: | 07.07.1999 | Language: | EN | [1999/27] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 02.12.1996 | Classification | IPC: | G06F7/52, G06F7/50 | [1997/01] | CPC: |
G06F7/5338 (EP,US);
G06F7/501 (EP,US);
G06F7/507 (EP,US);
H03K19/09448 (EP,US);
G06F2207/3884 (EP,US);
G06F2207/4812 (EP,US);
G06F2207/4816 (EP,US)
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| Former IPC [1996/43] | G06F7/52 | Designated contracting states | DE, ES, FR, GB, IT [1996/43] | Title | German: | Multiplizierer | [1996/43] | English: | Multiplier | [1996/43] | French: | Multiplieur | [1996/43] | Examination procedure | 05.06.1997 | Examination requested [1997/32] | 16.09.1998 | Despatch of communication of intention to grant (Approval: Yes) | 12.01.1999 | Communication of intention to grant the patent | 12.04.1999 | Fee for grant paid | 12.04.1999 | Fee for publishing/printing paid | Parent application(s) Tooltip | EP92921222.3 / EP0610259 | Opposition(s) | 08.04.2000 | No opposition filed within time limit [2000/26] | Fees paid | Renewal fee | 14.06.1996 | Renewal fee patent year 03 | 14.06.1996 | Renewal fee patent year 04 | 25.01.1997 | Renewal fee patent year 05 | 16.12.1997 | Renewal fee patent year 06 | 23.10.1998 | Renewal fee patent year 07 | Penalty fee | Additional fee for renewal fee | 31.10.1996 | 05 M06 Fee paid on 25.01.1997 | 31.10.1997 | 06 M06 Fee paid on 16.12.1997 |
| Opt-out from the exclusive Tooltip competence of the Unified Patent Court | See the Register of the Unified Patent Court for opt-out data | ||
| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | IT | 07.07.1999 | ES | 20.01.2000 | [2008/06] |
| Former [2004/04] | ES | 20.01.2000 | Documents cited: | Search | [Y] - WASER S, "High-speed monolithic multipliers for real-time digital signal processing", COMPUTER, OCT. 1978, USA, ISSN 0018-9162, vol. 11, no. 10, pages 19 - 29, XP002010631 [Y] 1,4,5 * figure 8 * DOI: http://dx.doi.org/10.1109/C-M.1978.217939 | [Y] - NORTH R C ET AL, "Beta-bit serial/parallel multipliers", JOURNAL OF VLSI SIGNAL PROCESSING, (19910501), vol. 2, no. 4, pages 219 - 233, XP000229137 [Y] 1,5 * paragraph [0005]; figure 6 * DOI: http://dx.doi.org/10.1007/BF00925467 | [A] - WARE F A ET AL, "64 bit monolithic floating point processors", IEEE JOURNAL OF SOLID-STATE CIRCUITS, OCT. 1982, USA, ISSN 0018-9200, vol. SC-17, no. 5, pages 898 - 907, XP002010632 [A] 1 * figure 6 * DOI: http://dx.doi.org/10.1109/JSSC.1982.1051837 | [A] - YOSHINO T ET AL, "A 100 MHz 64-tap FIR digital filter in a 0.8 mu m BiCMOS gate array", 1990 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE. DIGEST OF TECHNICAL PAPERS. (CAT. NO.90CH2824-1), SAN FRANCISCO, CA, USA, 14-16 FEB. 1990, 1990, NEW YORK, NY, USA, IEEE, USA, pages 114 - 115, XP000201848 [A] 2 * figure 4 * | [Y] - UYA M ET AL, "A CMOS floating point multiplier", IEEE JOURNAL OF SOLID-STATE CIRCUITS, OCT. 1984, USA, ISSN 0018-9200, vol. SC-19, no. 5, pages 697 - 702, XP002017779 [Y] 4 * paragraph [00IV]; figures 2,3,5 * DOI: http://dx.doi.org/10.1109/JSSC.1984.1052210 |