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EP0780888
European procedure
Extract from the Register of European Patents
EP About this file: EP0780888
| EP0780888 - Method of manufacturing a gate electrode for a MOS structure [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 13.12.2002 Database last updated on 24.01.2025 | Most recent event Tooltip | 13.12.2002 | No opposition filed within time limit | published on 29.01.2003 [2003/05] | Applicant(s) | For all designated states Infineon Technologies AG St.-Martin-Strasse 53 81669 München / DE | [2002/06] |
| Former [2001/05] | For all designated states Infineon Technologies AG St.-Martin-Strasse 53 81541 München / DE | ||
| Former [1997/26] | For all designated states SIEMENS AKTIENGESELLSCHAFT Wittelsbacherplatz 2 80333 München / DE | Inventor(s) | 01 /
Lustig, Bernhard, Dr. Unterhachinger Strasse 33a 81737 München / DE | [1997/26] | Representative(s) | Zedlitz, Peter, et al OSRAM GmbH Intellectual Property IP Postfach 22 13 17 80503 München / DE | [N/P] |
| Former [2001/05] | Zedlitz, Peter, Dipl.-Inf., et al Patentanwalt, Postfach 22 13 17 80503 München / DE | Application number, filing date | 96119052.7 | 27.11.1996 | [1997/26] | Priority number, date | DE1995148056 | 21.12.1995 Original published format: DE 19548056 | [1997/26] | Filing language | DE | Procedural language | DE | Publication | Type: | A2 Application without search report | No.: | EP0780888 | Date: | 25.06.1997 | Language: | DE | [1997/26] | Type: | A3 Search report | No.: | EP0780888 | Date: | 16.07.1997 | [1997/29] | Type: | B1 Patent specification | No.: | EP0780888 | Date: | 06.02.2002 | Language: | DE | [2002/06] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 29.05.1997 | Classification | IPC: | H01L21/28 | [1997/26] | CPC: |
H01L21/28132 (EP,US);
H01L21/28 (KR);
Y10S438/947 (EP,US)
| Designated contracting states | AT, DE, FR, GB, IE, IT [1997/26] | Title | German: | Verfahren zur Herstellung einer Gateelektrode für eine MOS-Struktur | [1997/26] | English: | Method of manufacturing a gate electrode for a MOS structure | [1997/26] | French: | Méthode de fabrication d'une électrode de porte pour une structure MOS | [1997/26] | Examination procedure | 22.10.1997 | Examination requested [1997/51] | 01.12.2000 | Despatch of communication of intention to grant (Approval: Yes) | 15.06.2001 | Communication of intention to grant the patent | 10.09.2001 | Fee for grant paid | 10.09.2001 | Fee for publishing/printing paid | Opposition(s) | 07.11.2002 | No opposition filed within time limit [2003/05] | Fees paid | Renewal fee | 17.11.1998 | Renewal fee patent year 03 | 18.11.1999 | Renewal fee patent year 04 | 20.11.2000 | Renewal fee patent year 05 | 19.11.2001 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [DA]US4358340 (FU HORNG-SEN) [DA] 1-3* column 2, line 53 - column 3, line 35; figures 1-5 *; | [A]EP0402296 (IBM [US]) [A] 1-3 * column 8, line 34 - column 9, line 22; figure 3 *; | [DA] - JOHNSON C ET AL, "METHOD FOR MAKING SUBMICRON DIMENSIONS IN STRUCTURES USING SIDEWALL IMAGE TRANSFER TECHNIQUES", IBM TECHNICAL DISCLOSURE BULLETIN, (19840201), vol. 26, no. 9, pages 4587 - 4589, XP002000221 [DA] 1,2 * the whole document * | by applicant | US4358340 | - C. JOHNSON ET AL., IBM TECHNICAL DISCLOSURE BULLETIN, (1984), vol. 26, no. 9, pages 4587 - 4589 |