EP0834817 - Programmed neural module [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 01.06.2001 Database last updated on 22.08.2024 | Most recent event Tooltip | 04.01.2008 | Lapse of the patent in a contracting state New state(s): IT | published on 06.02.2008 [2008/06] | Applicant(s) | For all designated states FINMECCANICA S.p.A. AZIENDA ANSALDO Piazza Carignano, 2 16128 Genova / IT | [2000/31] |
Former [1998/15] | For all designated states FINMECCANICA S.p.A. AZIENDA ANSALDO Piazza Carignano, 2 I-16128 Genova / IT | Inventor(s) | 01 /
Baratta, Daniela Salita dell'Orso, 10D/21 16143 Genova / IT | 02 /
Caviglia, Daniele Via Trento, 36/8 16145 Genova / IT | 03 /
Parenti, Riccardo Via alla Chiesa, 41 16030 Pieve Ligure, (Genova) / IT | 04 /
Valle, Maurizio Via Aurelia, 92 17025 Loano, (Savona) / IT | [1998/15] | Representative(s) | Perani, Aurelio, et al c/o JACOBACCI & PERANI S.p.A Via Senato 8 20121 Milano / IT | [N/P] |
Former [1998/17] | Perani, Aurelio, et al c/o JACOBACCI & PERANI S.p.A Via Visconti di Modrone, 7 20122 Milano / IT | ||
Former [1998/15] | Falcetti, Carlo, et al c/o JACOBACCI & PERANI S.p.A. Via Visconti di Modrone, 7 20122 Milano / IT | Application number, filing date | 96830500.3 | 01.10.1996 | [1998/15] | Filing language | IT | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0834817 | Date: | 08.04.1998 | Language: | EN | [1998/15] | Type: | B1 Patent specification | No.: | EP0834817 | Date: | 02.08.2000 | Language: | EN | [2000/31] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 14.04.1997 | Classification | IPC: | G06F15/80 | [1998/15] | CPC: |
G06N3/063 (EP)
| Designated contracting states | DE, GB, IT [1998/52] |
Former [1998/15] | AT, BE, CH, DE, DK, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE | Title | German: | Programmierter Neuronalmodul | [1998/15] | English: | Programmed neural module | [1998/15] | French: | Module neuronal programmé | [1998/15] | Examination procedure | 22.07.1998 | Examination requested [1998/38] | 09.10.1998 | Loss of particular rights, legal effect: designated state(s) | 18.01.1999 | Despatch of communication of loss of particular rights: designated state(s) AT, BE, CH, DK, ES, FI, FR, GR, IE, LI, LU, MC, NL, PT, SE | 18.03.1999 | Despatch of a communication from the examining division (Time limit: M04) | 09.07.1999 | Reply to a communication from the examining division | 14.09.1999 | Despatch of communication of intention to grant (Approval: Yes) | 18.01.2000 | Communication of intention to grant the patent | 03.04.2000 | Fee for grant paid | 03.04.2000 | Fee for publishing/printing paid | Opposition(s) | 03.05.2001 | No opposition filed within time limit [2001/29] | Fees paid | Renewal fee | 16.09.1998 | Renewal fee patent year 03 | 20.09.1999 | Renewal fee patent year 04 | Penalty fee | Penalty fee Rule 85a EPC 1973 | 06.11.1998 | AT   M01   Not yet paid | 06.11.1998 | BE   M01   Not yet paid | 06.11.1998 | CH   M01   Not yet paid | 06.11.1998 | DK   M01   Not yet paid | 06.11.1998 | ES   M01   Not yet paid | 06.11.1998 | FI   M01   Not yet paid | 06.11.1998 | FR   M01   Not yet paid | 06.11.1998 | GR   M01   Not yet paid | 06.11.1998 | IE   M01   Not yet paid | 06.11.1998 | LU   M01   Not yet paid | 06.11.1998 | MC   M01   Not yet paid | 06.11.1998 | NL   M01   Not yet paid | 06.11.1998 | PT   M01   Not yet paid | 06.11.1998 | SE   M01   Not yet paid |
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | IT | 02.08.2000 | GB | 02.11.2000 | DE | 03.11.2000 | [2008/06] |
Former [2002/13] | GB | 02.11.2000 | |
DE | 03.11.2000 | ||
Former [2002/12] | GB | 02.11.2000 | Documents cited: | Search | [Y]US4254474 (COOPER LEON N, et al) [Y] 1-3 * column 6, line 51 - column 9, line 65; figures 6,7 *; | [A]US5226092 (CHEN KAIHU [US]) [A] 1 * column 10, line 62 - column 13, line 6; figures 6,7 *; | [Y] - VERLEYSEN M ET AL, "AN ANALOG PROCESSOR ARCHITECTURE FOR A NEURAL NETWORK CLASSIFIER", IEEE MICRO, (19940601), vol. 14, no. 3, pages 16 - 28, XP000448653 [Y] 1-3 * page 19, column L, line 3 - line 32; figure 1 * DOI: http://dx.doi.org/10.1109/40.285221 | [A] - GRAF H P ET AL, "A NEURAL-NET BOARD SYSTEM FOR MACHINE VISION APPLICATIONS", PROCEEDINGS OF THE INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORK (IJCNN), SEATTLE, JULY 8 - 12, 1991, INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, (19910708), vol. 1, pages 481 - 486, XP000239692 [A] 1 * page 482, line 26 - line 30 * DOI: http://dx.doi.org/10.1109/IJCNN.1991.155226 | [A] - SHIMOKAWA Y ET AL, "A programmable parallel digital neurocomputer", IEICE TRANSACTIONS ON ELECTRONICS, JULY 1993, JAPAN, ISSN 0916-8524, vol. E76-C, no. 7, pages 1197 - 1205, XP000394462 [A] 1-4 * page 1199, column L, line 21 - page 1201, column R, line 11; figures 1-7 * |