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EP0864172
European procedure
Extract from the Register of European Patents
EP About this file: EP0864172
| EP0864172 - PROCESS FOR PRODUCING AN INTEGRATED CIRCUIT DEVICE WITH AT LEAST ONE MOS TRANSISTOR [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 09.08.2002 Database last updated on 31.08.2024 | Most recent event Tooltip | 09.08.2002 | No opposition filed within time limit | published on 25.09.2002 [2002/39] | Applicant(s) | For all designated states Infineon Technologies AG St.-Martin-Strasse 53 81669 München / DE | [2001/18] |
| Former [1998/38] | For all designated states SIEMENS AKTIENGESELLSCHAFT Wittelsbacherplatz 2 80333 München / DE | Inventor(s) | 01 /
SCHWALKE, Udo Gewerbestrasse 22 D-84431 Heldenstein / DE | [1998/38] | Representative(s) | Zedlitz, Peter, et al OSRAM GmbH Intellectual Property IP Postfach 22 13 17 80503 München / DE | [N/P] |
| Former [2001/18] | Zedlitz, Peter, Dipl.-Inf., et al Patentanwalt, Postfach 22 13 17 80503 München / DE | Application number, filing date | 96945866.0 | 07.11.1996 | [1998/38] | WO1996DE02121 | Priority number, date | DE1995144721 | 30.11.1995 Original published format: DE 19544721 | [1998/38] | Filing language | DE | Procedural language | DE | Publication | Type: | A2 Application without search report | No.: | WO9720336 | Date: | 05.06.1997 | Language: | DE | [1997/24] | Type: | A2 Application without search report | No.: | EP0864172 | Date: | 16.09.1998 | Language: | DE | The application published by WIPO in one of the EPO official languages on 05.06.1997 takes the place of the publication of the European patent application. | [1998/38] | Type: | B1 Patent specification | No.: | EP0864172 | Date: | 04.10.2001 | Language: | DE | [2001/40] | Search report(s) | International search report - published on: | EP | 28.08.1997 | Classification | IPC: | H01L21/28, H01L21/336 | [1998/38] | CPC: |
H01L21/84 (EP,US);
H01L21/18 (KR);
H01L29/66628 (EP)
| Designated contracting states | AT, DE, FR, GB, IE, IT, NL [1998/38] | Title | German: | VERFAHREN ZUR HERSTELLUNG EINER INTEGRIERTEN SCHALTUNGSANORDNUNG MIT MINDESTENS EINEM MOS-TRANSISTOR | [1998/38] | English: | PROCESS FOR PRODUCING AN INTEGRATED CIRCUIT DEVICE WITH AT LEAST ONE MOS TRANSISTOR | [1998/38] | French: | PROCEDE DE FABRICATION D'UN DISPOSITIF A CIRCUITS INTEGRES EQUIPE D'AU MOINS UN TRANSISTOR MOS | [1998/38] | Entry into regional phase | 19.05.1998 | National basic fee paid | 19.05.1998 | Designation fee(s) paid | 19.05.1998 | Examination fee paid | Examination procedure | 27.06.1997 | Request for preliminary examination filed International Preliminary Examining Authority: EP | 19.05.1998 | Examination requested [1998/38] | 21.05.1999 | Despatch of a communication from the examining division (Time limit: M06) | 09.11.1999 | Reply to a communication from the examining division | 12.12.2000 | Despatch of communication of intention to grant (Approval: Yes) | 06.04.2001 | Communication of intention to grant the patent | 20.06.2001 | Fee for grant paid | 20.06.2001 | Fee for publishing/printing paid | Opposition(s) | 05.07.2002 | No opposition filed within time limit [2002/39] | Fees paid | Renewal fee | 17.11.1998 | Renewal fee patent year 03 | 18.11.1999 | Renewal fee patent year 04 | 20.11.2000 | Renewal fee patent year 05 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Cited in | International search | [YA]EP0115131 (TOKYO SHIBAURA ELECTRIC CO [JP]) [Y] 1-3,5-8 * page 7 - page 9; figure 11 * [A] 4; | [A]EP0373893 (MITSUBISHI ELECTRIC CORP [JP]) [A] 1-8* the whole document *; | [YA]EP0442296 (HUGHES AIRCRAFT CO [US]) [Y] 1-3,5-8 * column 3, line 58 - column 5, line 47; figures 1,2 * [A] 4; | [YA]US5144390 (MATLOUBIAN MISHEL [US]) [Y] 1-3,5-8 * column 4, line 4 - column 5, line 31; figures 1,2 * [A] 4; | [YA]US5177028 (MANNING MONTE [US]) [Y] 1-3,5-8 * column 4, line 3 - column 5, line 31; figures 8-13 * [A] 4; | [YA]US5294823 (EKLUND ROBERT H [US], et al) [Y] 1-3,5-8 * column 3, line 26 - column 6, line 5; figure 11 * [A] 4 |