EP0817252 - Method for manufacturing surface channel type P-channel MOS transistor while supressing P-type impurity penetration [Right-click to bookmark this link] | Status | The application has been withdrawn Status updated on 11.07.2003 Database last updated on 02.09.2024 | Most recent event Tooltip | 11.07.2003 | Withdrawal of application | published on 27.08.2003 [2003/35] | Applicant(s) | For all designated states NEC Corporation 7-1, Shiba 5-chome Minato-ku Tokyo 108-8001 / JP | [N/P] |
Former [1998/02] | For all designated states NEC CORPORATION 7-1, Shiba 5-chome Minato-ku Tokyo / JP | Inventor(s) | 01 /
Togo, Mitsuhiro NEC Corporation, 7-1, Shiba 5-chome Minato-ku, Tokyo / JP | [1998/02] | Representative(s) | Baronetzky, Klaus, et al Splanemann Patentanwälte Partnerschaft Rumfordstrasse 7 80469 München / DE | [N/P] |
Former [1998/02] | Baronetzky, Klaus, Dipl.-Ing., et al Patentanwälte Dipl.-Ing. R. Splanemann, Dr. B. Reitzner, Dipl.-Ing. K. Baronetzky Tal 13 80331 München / DE | Application number, filing date | 97110519.2 | 26.06.1997 | [1998/02] | Priority number, date | JP19960167284 | 27.06.1996 Original published format: JP 16728496 | [1998/02] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0817252 | Date: | 07.01.1998 | Language: | EN | [1998/02] | Type: | A3 Search report | No.: | EP0817252 | Date: | 04.08.1999 | [1999/31] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 18.06.1999 | Classification | IPC: | H01L21/336, H01L29/78, H01L21/28 | [1998/19] | CPC: |
H01L21/2652 (EP,US);
H01L21/18 (KR);
H01L21/28176 (EP,US);
H01L21/28202 (EP,US);
H01L29/4916 (EP,US);
H01L29/518 (EP,US);
H01L29/6659 (EP,US);
H01L29/7833 (EP,US);
H01L21/26506 (US);
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Former IPC [1998/02] | H01L21/336, H01L29/78 | Designated contracting states | DE, GB [1998/02] | Title | German: | Verfahren zum Herstellen von p-Kanal MOS Transistoren mit Oberflächenkanal wobei das Eindringen von p-Typ Verunreinigungen verhindert wird | [1998/02] | English: | Method for manufacturing surface channel type P-channel MOS transistor while supressing P-type impurity penetration | [1998/02] | French: | Procédé de fabrication d'un transistor MOS à canal p superficiel par suppression de la pénétration des impuretés de type p | [1998/02] | Examination procedure | 01.07.1999 | Examination requested [1999/35] | 29.11.2002 | Despatch of a communication from the examining division (Time limit: M06) | 30.05.2003 | Reply to a communication from the examining division | 27.06.2003 | Application withdrawn by applicant [2003/35] | Fees paid | Renewal fee | 28.05.1999 | Renewal fee patent year 03 | 05.06.2000 | Renewal fee patent year 04 | 29.05.2001 | Renewal fee patent year 05 | 05.06.2002 | Renewal fee patent year 06 | 30.05.2003 | Renewal fee patent year 07 |
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X]JPH0278229 ; | [A]US4764478 (HIRUTA YOICHI [JP]) [A] 5-11* column 4, line 22 - column 5, line 48 *; | [XY]US5393676 (ANJUM MOHAMMED [US], et al) [X] 1 * abstract * * column 6, line 28 - line 53 * [Y] 2-4; | [Y]US5464792 (TSENG HSING-HUANG [US], et al) [Y] 2-4 * column 3, line 43 - column 4, line 14; figures 1-4 * * column 6, line 53 - column 7, line 29; figure 9 *; | [X] - PATENT ABSTRACTS OF JAPAN, (19900604), vol. 014, no. 257, Database accession no. (E - 0936), & JP02078229 A 19900319 (NEC CORP) [X] 1-4 * abstract * | [X] - SHIMIZU S ET AL, "IMPACT OF NITROGEN IMPLANTATION ON HIGHLY RELIABLE SUB-QUARTER MICRON LDD MOSFETS", INTERNATIONAL CONFERENCE ON SOLID STATE DEVICES AND MATERIALS, (19950821), pages 219 - 221, XP000544607 [X] 1 * page 219, column L; figure 1A * | [X] - SUN W T ET AL, "Process optimization for preventing boron-penetration using P or As co-implant in P-poly gate of P-MOSFETs", 1995 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS. PROCEEDINGS OF TECHNICAL PAPERS (CAT. NO.95TH8104), 1995 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS. PROCEEDINGS OF TECHNICAL PAPERS, TAIPEI, TAIWA, ISBN 0-7803-2773-X, 1995, New York, NY, USA, IEEE, USA, pages 40 - 43, XP002098813 [X] 5-11 * abstract * | [X] - PFIESTER J R ET AL, "The effects of boron penetration on p/sup +/ polysilicon gated PMOS devices", IEEE TRANSACTIONS ON ELECTRON DEVICES, AUG. 1990, USA, ISSN 0018-9383, vol. 37, no. 8, pages 1842 - 1851, XP000148765 [X] 5-11 * abstract * DOI: http://dx.doi.org/10.1109/16.57135 |