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Extract from the Register of European Patents

EP About this file: EP0841704

EP0841704 - Semiconductor transistor device and method of manufacturing the same [Right-click to bookmark this link]
StatusThe application is deemed to be withdrawn
Status updated on  25.06.1999
Database last updated on 03.10.2024
Most recent event   Tooltip13.06.2008Change - representativepublished on 16.07.2008  [2008/29]
Applicant(s)For all designated states
Paul-Drude-Institut für Festkörperelektronik
Hausvogteiplatz 5-7
10117 Berlin / DE
[1998/20]
Inventor(s)01 / Friedland, K.-J., Dr.
Lehnitzstrasse 49C
12623 Berlin / DE
02 / Hey, R., Dr.
Märkische Allee 222
12679 Berlin / DE
03 / Kostial, H., Dr.
Geschwister-Scholl-Strasse 5
10117 Berlin / DE
04 / Höricke, M.
Ernst-Thälmann-Strasse 22
16341 Schwanebeck / DE
05 / Ploog, K.H., Prof. Dr.
Ludwig-Jahn-Strasse 6
15566 Schöneiche / DE
[1998/20]
Representative(s)Morgan, James Garnet, et al
Manitz, Finsterwald & Partner GbR
Postfach 31 02 20
80102 München / DE
[N/P]
Former [2008/29]Morgan, James Garnet, et al
Manitz, Finsterwald & Partner GbR Postfach 31 02 20
80102 München / DE
Former [1998/20]Morgan, James G., et al
Robert-Koch-Strasse 1
80538 München / DE
Application number, filing date97113111.530.07.1997
[1998/20]
Priority number, dateEP1996011788407.11.1996         Original published format: EP 96117884
[1998/20]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report 
No.:EP0841704
Date:13.05.1998
Language:EN
[1998/20]
Search report(s)(Supplementary) European search report - dispatched on:EP19.11.1997
ClassificationIPC:H01L29/15, H01L29/36, H01L29/778, H01L29/775, H01L21/335
[1998/20]
CPC:
B82Y10/00 (EP); H01L29/155 (EP); H01L29/66462 (EP);
H01L29/66469 (EP); H01L29/775 (EP); H01L29/7785 (EP);
H01L29/2003 (EP); H01L29/365 (EP) (-)
Designated contracting states(deleted) [1999/04]
Former [1998/20]AT,  BE,  CH,  DE,  DK,  ES,  FI,  FR,  GB,  GR,  IE,  IT,  LI,  LU,  MC,  NL,  PT,  SE 
TitleGerman:Transistorhalbleiterbauelement und Verfahren zu dessen Herstellung[1998/20]
English:Semiconductor transistor device and method of manufacturing the same[1998/20]
French:Dispositif semi-conducteur à transistor et méthode de fabrication[1998/20]
Examination procedure14.11.1998Application deemed to be withdrawn, date of legal effect  [1999/32]
12.03.1999Despatch of communication that the application is deemed to be withdrawn, reason: examination fee not paid in time  [1999/32]
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:Search[XY]JPS6235678  ;
 [X]JPS62136882  ;
 [DY]EP0394757  (MAX PLANCK GESELLSCHAFT) [DY] 6,12-14 * the whole document *;
 [DA]US4882609  (SCHUBERT ERDMANN ET AL) [DA] 1,7 * column 9, line 53 - column 10, line 43; figures 1J,1G *;
 [PX]  - FRIEDLAND K -J ET AL, "New concept for the reduction of impurity scattering in remotely doped GaAs quantum wells", PHYSICAL REVIEW LETTERS, 25 NOV. 1996, APS, USA, ISSN 0031-9007, vol. 77, no. 22, pages 4616 - 4619, XP002044440 [PX] 1-14 * the whole document *
 [XY]  - PATENT ABSTRACTS OF JAPAN, (19870714), vol. 011, no. 217, Database accession no. (E - 523), & JP62035678 A 19870216 (FUJITSU LTD) [X] 1-5,7-11 * abstract * [Y] 6,12-14
 [X]  - PATENT ABSTRACTS OF JAPAN, (19871126), vol. 011, no. 363, Database accession no. (E - 560), & JP62136882 A 19870619 (FUJITSU LTD) [X] 1 * abstract *
 [A]  - NGUYEN L D ET AL, "INFLUENCE OF QUANTUM-WELL WIDTH ON DEVICE PERFORMANCE OF AL0.30GA0.70AS/INP0.25GA0.75AS (ON GAAS) MODFET'S", IEEE TRANSACTIONS ON ELECTRON DEVICES, (19890501), vol. 36, no. 5, pages 833 - 838, XP000099014 [A] 5,11

DOI:   http://dx.doi.org/10.1109/16.299663
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