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Extract from the Register of European Patents

EP About this file: EP0833343

EP0833343 - A NOR gate applied to a sub-decoder of a semiconductor memory [Right-click to bookmark this link]
StatusThe application has been withdrawn
Status updated on  19.05.2006
Database last updated on 02.11.2024
Most recent event   Tooltip19.05.2006Withdrawal of applicationpublished on 21.06.2006  [2006/25]
Applicant(s)For all designated states
NEC Corporation
7-1, Shiba 5-chome Minato-ku
Tokyo 108-8001 / JP
For all designated states
NEC Electronics Corporation
1753 Shimonumabe Nakahara-ku
Kawasaki, Kanagawa 211-8668 / JP
[N/P]
Former [2003/15]For all designated states
NEC CORPORATION
7-1, Shiba 5-chome Minato-ku
Tokyo / JP
For all designated states
NEC Electronics Corporation
1753 Shimonumabe, Nakahara-ku
Kawasaki, Kanagawa 211-8668 / JP
Former [1998/14]For all designated states
NEC CORPORATION
7-1, Shiba 5-chome Minato-ku
Tokyo / JP
Inventor(s)01 / Miki, Atsunori
NEC Corporation, 7-1, Shiba 5-chome
Minato-ku, Tokyo / JP
[1998/14]
Representative(s)Glawe, Delfs, Moll
Partnerschaft mbB von
Patent- und Rechtsanwälten
Postfach 26 01 62
80058 München / DE
[N/P]
Former [1998/14]Glawe, Delfs, Moll & Partner
Patentanwälte Postfach 26 01 62
80058 München / DE
Application number, filing date97116881.029.09.1997
[1998/14]
Priority number, dateJP1996027893430.09.1996         Original published format: JP 27893496
[1998/14]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0833343
Date:01.04.1998
Language:EN
[1998/14]
Type: A3 Search report 
No.:EP0833343
Date:17.08.2005
[2005/33]
Search report(s)(Supplementary) European search report - dispatched on:EP05.07.2005
ClassificationIPC:G11C8/00
[1998/14]
CPC:
G11C11/418 (EP); G11C11/40 (KR); G11C8/10 (EP);
H03K19/0948 (EP)
Designated contracting statesDE,   FR,   GB [2006/19]
Former [1998/14]AT,  BE,  CH,  DE,  DK,  ES,  FI,  FR,  GB,  GR,  IE,  IT,  LI,  LU,  MC,  NL,  PT,  SE 
TitleGerman:An einem Subdekodierer eines Halbleiterspeichers angekoppeltes NOR-Gatter[1998/14]
English:A NOR gate applied to a sub-decoder of a semiconductor memory[1998/14]
French:Porte NON/OU couplée à un sous-décodeur d'une mémoire à semi-conducteurs[1998/14]
Examination procedure22.07.2005Examination requested  [2005/38]
23.03.2006Despatch of a communication from the examining division (Time limit: M04)
02.05.2006Application withdrawn by applicant  [2006/25]
Fees paidRenewal fee
20.09.1999Renewal fee patent year 03
20.09.2000Renewal fee patent year 04
20.09.2001Renewal fee patent year 05
18.09.2002Renewal fee patent year 06
22.09.2003Renewal fee patent year 07
21.09.2004Renewal fee patent year 08
20.09.2005Renewal fee patent year 09
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Documents cited:Search[YA]US4618784  (CHAPPELL BARBARA A [US], et al);
 [A]US4731761  (KOBAYASHI TOSHIFUMI [JP]);
 [YA]US5077495  (TORIMARU YASUO [JP], et al)
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.