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EP0851587
European procedure
Extract from the Register of European Patents
EP About this file: EP0851587
| EP0851587 - MOS logic circuit [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 02.07.2004 Database last updated on 26.03.2026 | Most recent event Tooltip | 02.07.2004 | No opposition filed within time limit | published on 18.08.2004 [2004/34] | Applicant(s) | For all designated states Sharp Kabushiki Kaisha 22-22 Nagaike-cho Abeno-ku Osaka-shi Osaka-fu 545-0013 / JP | [N/P] |
| Former [2003/35] | For all designated states SHARP KABUSHIKI KAISHA 22-22 Nagaike-cho, Abeno-ku Osaka-shi, Osaka-fu 545-0013 / JP | ||
| Former [1998/27] | For all designated states SHARP KABUSHIKI KAISHA 22-22 Nagaike-cho, Abeno-ku Osaka-shi, Osaka-fu 545 / JP | Inventor(s) | 01 /
Kioi, Kazumasa 5-35-507, 1-chome Oka Fujiidera-shi, Osaka 583 / JP | [1998/27] | Representative(s) | Müller, Frithjof E. Müller Hoffmann & Partner Patentanwälte Innere Wiener Strasse 17 81667 München / DE | [N/P] |
| Former [1998/27] | Müller, Frithjof E., Dipl.-Ing. Patentanwälte MÜLLER & HOFFMANN, Innere Wiener Strasse 17 81667 München / DE | Application number, filing date | 97118705.9 | 28.10.1997 | [1998/27] | Priority number, date | JP19960346028 | 25.12.1996 Original published format: JP 34602896 | [1998/27] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0851587 | Date: | 01.07.1998 | Language: | EN | [1998/27] | Type: | A3 Search report | No.: | EP0851587 | Date: | 01.09.1999 | [1999/35] | Type: | B1 Patent specification | No.: | EP0851587 | Date: | 27.08.2003 | Language: | EN | [2003/35] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 21.07.1999 | Classification | IPC: | H03K19/00 | [1998/27] | CPC: |
H03K19/0019 (EP,US);
H10D84/0165 (KR);
H03K19/0963 (EP,US);
H10D84/038 (KR);
H10D84/859 (EP,US)
| Designated contracting states | DE, FR, GB [2000/19] |
| Former [1998/27] | AT, BE, CH, DE, DK, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE | Title | German: | Logische MOS-Schaltung | [1998/27] | English: | MOS logic circuit | [1998/27] | French: | Circuit logique MOS | [1998/27] | Examination procedure | 07.09.1999 | Examination requested [1999/44] | 19.11.2002 | Communication of intention to grant the patent | 19.03.2003 | Fee for grant paid | 19.03.2003 | Fee for publishing/printing paid | Opposition(s) | 28.05.2004 | No opposition filed within time limit [2004/34] | Fees paid | Renewal fee | 21.10.1999 | Renewal fee patent year 03 | 24.10.2000 | Renewal fee patent year 04 | 10.10.2001 | Renewal fee patent year 05 | 29.10.2002 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [DA] YONG MOON ET AL: "EFFICIENT CHARGE RECOVERY LOGIC", 1995 SYMPOSIUM ON VLSI CIRCUITS, KYOTO, JUNE 8 - 10, 1995, 8 June 1995 (1995-06-08), INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 129/130, XP000557835, ISBN: 0-7803-2600-8 [DA] 1-3,7-12,15,16 * page 129 - page 130 * | [A] KUGE S ET AL: "SOI-DRAM CIRCUIT TECHNOLOGIES FOR LOW POWER HIGH SPEED MULTI-GIGA SCALE MEMORIES", 1995 SYMPOSIUM ON VLSI CIRCUITS, KYOTO, JUNE 8 - 10, 1995, 8 June 1995 (1995-06-08), INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 103/104, XP000557822, ISBN: 0-7803-2600-8 [A] 4,13,17,18 * page 103; figure 104 * |