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Extract from the Register of European Patents

EP About this file: EP0890184

EP0890184 - A METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR LAYER OF SiC [Right-click to bookmark this link]
Former [1999/02]A METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR LAYER OF SiC AND SUCH A DEVICE
[2009/09]
StatusNo opposition filed within time limit
Status updated on  14.05.2010
Database last updated on 18.11.2024
Most recent event   Tooltip07.09.2012Lapse of the patent in a contracting state
New state(s): SE
published on 10.10.2012  [2012/41]
Applicant(s)For all designated states
Cree, Inc.
4600 Silicon Drive
Durham, NC 27703 / US
[N/P]
Former [2004/11]For all designated states
CREE, INC.
4600 Silicon Drive
Durham, NC 27703 / US
Former [1999/02]For all designated states
ABB RESEARCH LTD.
P.O. Box 8131
8050 Zürich / CH
Inventor(s)01 / ROTTNER, Kurt
Langelandsgatan 12
S-164 43 Kista / SE
[1999/02]
Representative(s)Olsson, Jan, et al
Bjerkéns Patentbyrå KB
P.O.Box 1274
801 37 Gävle / SE
[N/P]
Former [1999/02]Olsson, Jan, et al
Bjerkéns Patentbyra KB P.O.Box 1274
801 37 Gävle / SE
Application number, filing date97915823.526.03.1997
[1999/02]
WO1997SE00533
Priority number, dateSE1996000117427.03.1996         Original published format: SE 9601174
[1999/02]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report
No.:WO9736318
Date:02.10.1997
Language:EN
[1997/42]
Type: A2 Application without search report 
No.:EP0890184
Date:13.01.1999
Language:EN
The application published by WIPO in one of the EPO official languages on 02.10.1997 takes the place of the publication of the European patent application.
[1999/02]
Type: B1 Patent specification 
No.:EP0890184
Date:08.07.2009
Language:EN
[2009/28]
Search report(s)International search report - published on:SE04.12.1997
ClassificationIPC:H01L21/00
[1999/02]
CPC data not yet available
Designated contracting statesDE,   FR,   GB,   IT,   SE [1999/02]
TitleGerman:HERSTELLUNGSVERFAHREN FÜR EINE HALBLEITERANORDNUNG MIT EINER SiC SCHICHT[2009/09]
English:A METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR LAYER OF SiC[2009/09]
French:PROCEDE DE FABRICATION D'UN COMPOSANT A SEMI-CONDUCTEUR POSSEDANT UNE COUCHE DE SEMI-CONDUCTEUR EN SiC ET[2009/09]
Former [1999/02]HERSTELLUNGSVERFAHREN FÜR EINE HALBLEITERANORDNUNG MIT EINER SiC SCHICHT UND DEREN ANORDNUNG
Former [1999/02]A METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR LAYER OF SiC AND SUCH A DEVICE
Former [1999/02]PROCEDE DE FABRICATION D'UN COMPOSANT A SEMI-CONDUCTEUR POSSEDANT UNE COUCHE DE SEMI-CONDUCTEUR EN SiC ET COMPOSANT
Entry into regional phase28.09.1998National basic fee paid 
28.09.1998Designation fee(s) paid 
28.09.1998Examination fee paid 
Examination procedure19.09.1997Request for preliminary examination filed
International Preliminary Examining Authority: SE
28.09.1998Examination requested  [1999/02]
12.12.2002Despatch of a communication from the examining division (Time limit: M06)
19.06.2003Reply to a communication from the examining division
17.02.2005Date of oral proceedings
22.02.2005Minutes of oral proceedings despatched
05.01.2006Despatch of communication that the application is refused, reason: substantive examination {1}
03.02.2009Communication of intention to grant the patent
18.05.2009Fee for grant paid
18.05.2009Fee for publishing/printing paid
Appeal following examination06.03.2006Appeal received No.  T0427/06
06.03.2006Statement of grounds filed
09.10.2008Result of appeal procedure: remittal for grant
09.10.2008Date of oral proceedings
15.10.2008Minutes of oral proceedings despatched
09.10.2008Date of oral proceedings
09.09.2008Date of oral proceedings
Opposition(s)09.04.2010No opposition filed within time limit [2010/24]
Fees paidRenewal fee
11.03.1999Renewal fee patent year 03
13.03.2000Renewal fee patent year 04
16.03.2001Renewal fee patent year 05
13.03.2002Renewal fee patent year 06
11.03.2003Renewal fee patent year 07
15.03.2004Renewal fee patent year 08
14.03.2005Renewal fee patent year 09
09.03.2006Renewal fee patent year 10
14.03.2007Renewal fee patent year 11
14.03.2008Renewal fee patent year 12
13.03.2009Renewal fee patent year 13
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Lapses during opposition  TooltipSE08.07.2009
GB26.03.2010
[2012/41]
Former [2011/28]GB26.03.2010
Cited inInternational search[A]US5021851  (HAKEN ROGER A [US], et al);
 [A]US4914500  (LIU RUICHEN [US], et al);
 [A]US4851360  (HAKEN ROGER A [US], et al);
 [A]US4801555  (HOLLY PATRICK J [US], et al)
ExaminationGB1201428
 GB1397305
 US5322805
 GB1303660
    - CARL-MIKAEL ZETTERLING, Process technology for silicon devices, LONDON, UK, THE INSTITUTION OF ELECTRICAL ENGINEERS * pages 74-76 *
    - The Encyclopaedia of Materials: Science and Technology, ELSEVIER SCIENCE LTD. * pages 8505-8519 *
    - CAPANO M.A. ET AL, "Phosphorous Implantation into 4H-Silicon Carbide", JOURNAL OF ELETRONIC MATERIALS, (2000), vol. 29, no. 2, page 210
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.