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Extract from the Register of European Patents

EP About this file: EP0928486

EP0928486 - DEVICE AND METHOD FOR TESTING INTEGRATED CIRCUIT DICE IN AN INTEGRATED CIRCUIT MODULE [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  21.09.2002
Database last updated on 29.10.2024
Most recent event   Tooltip18.01.2008Lapse of the patent in a contracting state
New state(s): IT
published on 20.02.2008  [2008/08]
Applicant(s)For all designated states
Micron Technology, Inc.
8000 South Federal Way
Boise, ID 83707-0006 / US
[N/P]
Former [1999/28]For all designated states
MICRON TECHNOLOGY, INC.
8000 South Federal Way
Boise, ID 83707-0006 / US
Inventor(s)01 / FARNWORTH, Warren, M.
2004 S. Banner
Nampa, ID 83686-7271 / US
02 / WARK, James, M.
5718 W. Drawbridge Drive
Boise, ID 83703 / US
03 / NELSON, Eric, S.
3539 Buckboard Way
Boise, ID 83713 / US
04 / DUESMAN, Kevin, G.
4884 S. Suntree Way
Boise, ID 83706 / US
[1999/28]
Representative(s)Ottevangers, Sietse Ulbe, et al
Vereenigde, Postbus 87930
2508 DH Den Haag / NL
[N/P]
Former [1999/28]Ottevangers, Sietse Ulbe, et al
Vereenigde Octrooibureaux Nieuwe Parklaan 97
2587 BN 's-Gravenhage / NL
Application number, filing date97938416.120.08.1997
[1999/28]
WO1997US14564
Priority number, dateUS1996071817319.09.1996         Original published format: US 718173
[1999/28]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report
No.:WO9812706
Date:26.03.1998
Language:EN
[1998/12]
Type: A1 Application with search report 
No.:EP0928486
Date:14.07.1999
Language:EN
The application published by WIPO in one of the EPO official languages on 26.03.1998 takes the place of the publication of the European patent application.
[1999/28]
Type: B1 Patent specification 
No.:EP0928486
Date:14.11.2001
Language:EN
[2001/46]
Search report(s)International search report - published on:EP26.03.1998
ClassificationIPC:G11C29/00, G06F11/267
[1999/28]
CPC:
H01L22/22 (EP,US); G11C29/00 (KR); G11C29/46 (EP,US);
G11C29/785 (EP,US); G11C29/80 (EP,US); G11C29/808 (EP,US);
G01R31/2884 (EP,US); H01L2224/48091 (EP,US); H04J2203/0062 (EP,US) (-)
C-Set:
H01L2224/48091, H01L2924/00014 (EP,US)
Designated contracting statesAT,   BE,   CH,   DE,   DK,   ES,   FI,   FR,   GB,   GR,   IE,   IT,   LI,   LU,   MC,   NL,   PT,   SE [1999/28]
Extension statesAL06.04.1999
LT06.04.1999
LV06.04.1999
RO06.04.1999
SI06.04.1999
TitleGerman:VERFAHREN UND VORRICHTUNG ZUM PRÜFEN INTEGRIERTER SCHALTKREISCHIPS IN EINEM INTEGRIERTEN SCHALTKREISMODUL[1999/28]
English:DEVICE AND METHOD FOR TESTING INTEGRATED CIRCUIT DICE IN AN INTEGRATED CIRCUIT MODULE[1999/28]
French:DISPOSITIF ET PROCEDE D'ESSAI DES DES D'UN CIRCUIT INTEGRE DANS UN MODULE DE CIRCUIT INTEGRE[1999/28]
Entry into regional phase06.04.1999National basic fee paid 
06.04.1999Designation fee(s) paid 
06.04.1999Examination fee paid 
Examination procedure14.04.1998Request for preliminary examination filed
International Preliminary Examining Authority: EP
06.04.1999Examination requested  [1999/28]
09.09.1999Despatch of a communication from the examining division (Time limit: M06)
13.04.2000Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time
22.06.2000Reply to a communication from the examining division
08.02.2001Despatch of communication of intention to grant (Approval: Yes)
28.03.2001Communication of intention to grant the patent
28.06.2001Fee for grant paid
28.06.2001Fee for publishing/printing paid
Opposition(s)15.08.2002No opposition filed within time limit [2002/45]
Request for further processing for:22.06.2000Request for further processing filed
22.06.2000Full payment received (date of receipt of payment)
Request granted
10.07.2000Decision despatched
Fees paidRenewal fee
04.08.1999Renewal fee patent year 03
03.08.2000Renewal fee patent year 04
21.08.2001Renewal fee patent year 05
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipAT14.11.2001
BE14.11.2001
CH14.11.2001
FI14.11.2001
FR14.11.2001
GR14.11.2001
IT14.11.2001
LI14.11.2001
NL14.11.2001
DK14.02.2002
PT14.02.2002
SE14.02.2002
ES30.05.2002
[2008/08]
Former [2006/14]AT14.11.2001
BE14.11.2001
CH14.11.2001
FI14.11.2001
FR14.11.2001
GR14.11.2001
LI14.11.2001
NL14.11.2001
DK14.02.2002
PT14.02.2002
SE14.02.2002
ES30.05.2002
Former [2004/04]AT14.11.2001
BE14.11.2001
CH14.11.2001
FI14.11.2001
GR14.11.2001
LI14.11.2001
NL14.11.2001
DK14.02.2002
PT14.02.2002
SE14.02.2002
ES30.05.2002
Former [2003/46]AT14.11.2001
BE14.11.2001
CH14.11.2001
FI14.11.2001
GR14.11.2001
LI14.11.2001
NL14.11.2001
DK14.02.2002
PT14.02.2002
SE14.02.2002
Former [2003/09]AT14.11.2001
BE14.11.2001
CH14.11.2001
FI14.11.2001
GR14.11.2001
LI14.11.2001
NL14.11.2001
PT14.02.2002
SE14.02.2002
Former [2003/06]BE14.11.2001
CH14.11.2001
FI14.11.2001
GR14.11.2001
LI14.11.2001
NL14.11.2001
PT14.02.2002
SE14.02.2002
Former [2003/01]CH14.11.2001
FI14.11.2001
GR14.11.2001
LI14.11.2001
PT14.02.2002
SE14.02.2002
Former [2002/49]FI14.11.2001
GR14.11.2001
PT14.02.2002
SE14.02.2002
Former [2002/48]FI14.11.2001
PT14.02.2002
SE14.02.2002
Former [2002/33]FI14.11.2001
SE14.02.2002
Former [2002/27]SE14.02.2002
Cited inInternational search[A]EP0218852  (SIEMENS AG [DE]) [A] 1,3-5,14-16,19-21 * column 2, line 34 - column 3, line 17 * * column 3, line 29 - line 41 ** figures 1,2,4 *;
 [YA]EP0584739  (TOSHIBA KK [JP]) [Y] 19 * abstract * * column 1, line 10 - column 2, line 20 * [A] 1,2,9,12-14,18;
 [XAY]US5305267  (HARAGUCHI YOSHIYUKI [JP], et al) [X] 1-5,7,9,10,12,14-18 * column A * * column 7, line 28 - column 8, line 54 * * column 9, line 26 - line 65 * * column 10, line 10 - line 30 * * figures 1,2 * [A] 8,11,20,21 [Y] 19
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.