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EP0852380
European procedure
Extract from the Register of European Patents
EP About this file: EP0852380
| EP0852380 - Variable latency memory circuit [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 18.02.2005 Database last updated on 07.10.2024 | Most recent event Tooltip | 26.06.2009 | Change - representative | published on 29.07.2009 [2009/31] | Applicant(s) | For all designated states Texas Instruments Incorporated 7839 Churchill Way Mail Station 3999 Dallas, Texas 75251 / US | [N/P] |
| Former [1998/28] | For all designated states Texas Instruments Incorporated 7839 Churchill Way, Mail Station 3999 Dallas, Texas 75251 / US | Inventor(s) | 01 /
Thurston, Paulette 2221 Amy Lane Plano, Texas 75074 / US | [1998/28] | Representative(s) | Degwert, Hartmut, et al Prinz & Partner Rundfunkplatz 2 80335 München / DE | [N/P] |
| Former [2009/31] | Degwert, Hartmut, et al Prinz & Partner GbR Rundfunkplatz 2 80335 München / DE | ||
| Former [2003/12] | Degwert, Hartmut, Dipl.-Phys., et al Prinz & Partner GbR, Manzingerweg 7 81241 München / DE | ||
| Former [1998/28] | Schwepfinger, Karl-Heinz, Dipl.-Ing. Prinz & Partner, Manzingerweg 7 81241 München / DE | Application number, filing date | 98100014.4 | 02.01.1998 | [1998/28] | Priority number, date | US19970034470P | 02.01.1997 Original published format: US 34470 P | [1998/28] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0852380 | Date: | 08.07.1998 | Language: | EN | [1998/28] | Type: | A3 Search report | No.: | EP0852380 | Date: | 01.09.1999 | [1999/35] | Type: | B1 Patent specification | No.: | EP0852380 | Date: | 14.04.2004 | Language: | EN | [2004/16] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 20.07.1999 | Classification | IPC: | G11C7/00 | [1998/28] | CPC: |
G11C7/106 (EP,US);
G11C11/407 (KR);
G11C7/1018 (EP,US);
G11C7/1051 (EP,US);
G11C7/1066 (EP,US);
G11C7/1072 (EP,US);
G11C7/1078 (EP,US);
G11C7/1087 (EP,US);
G11C7/22 (EP,US);
G11C8/18 (EP,US)
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| Designated contracting states | DE, FR, GB, IT, NL [2000/19] |
| Former [1998/28] | AT, BE, CH, DE, DK, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE | Title | German: | Speicherschaltung mit variabler Latenz | [1998/28] | English: | Variable latency memory circuit | [1998/28] | French: | Circuit de mémoire à latence variable | [1998/28] | Examination procedure | 05.04.2000 | Examination requested [2000/22] | 07.06.2002 | Despatch of a communication from the examining division (Time limit: M06) | 16.12.2002 | Reply to a communication from the examining division | 31.10.2003 | Communication of intention to grant the patent | 06.02.2004 | Fee for grant paid | 06.02.2004 | Fee for publishing/printing paid | Opposition(s) | 17.01.2005 | No opposition filed within time limit [2005/14] | Fees paid | Renewal fee | 27.01.2000 | Renewal fee patent year 03 | 30.01.2001 | Renewal fee patent year 04 | 28.01.2002 | Renewal fee patent year 05 | 30.01.2003 | Renewal fee patent year 06 | 26.01.2004 | Renewal fee patent year 07 | Penalty fee | Penalty fee Rule 85b EPC 1973 | 16.03.2000 | M01 Fee paid on 05.04.2000 |
| Opt-out from the exclusive Tooltip competence of the Unified Patent Court | See the Register of the Unified Patent Court for opt-out data | ||
| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | IT | 14.04.2004 | NL | 14.04.2004 | [2008/08] |
| Former [2006/13] | NL | 14.04.2004 | Documents cited: | Search | [E]EP0818787 (TEXAS INSTRUMENTS INC [US], et al) [E] 1-15 * figure 18 *; | [E]EP0831493 (TEXAS INSTRUMENTS INC [US], et al) [E] 1-15 * figure 18 *; | [XY]EP0591009 (SAMSUNG ELECTRONICS CO LTD [KR]) [X] 1-9,11-14 * figures 3,4,13,23; table 1 * [Y] 10,15; | [X]US5544124 (ZAGAR PAUL S [US], et al) [X] 1-6,8,11,13 * figure 2 *; | [Y]US5568445 (PARK CHUROO [KR], et al) [Y] 10,15 * figures 1,2C *; | [A]EP0605887 (TOSHIBA KK [JP]) [A] 1-15 * figures 1,3,7,12 *; | [A]US5517462 (IWAMOTO HISASHI [JP], et al) [A] 3,4,6 * figure 32 * |