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EP0921639
European procedure
Extract from the Register of European Patents
EP About this file: EP0921639
| EP0921639 - Dynamic logic gate with relaxed timing requirements and output state holding [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 02.06.2006 Database last updated on 12.11.2024 | Most recent event Tooltip | 02.06.2006 | No opposition filed within time limit | published on 05.07.2006 [2006/27] | Applicant(s) | For all designated states Hewlett-Packard Company 3000 Hanover Street Palo Alto, CA 94304 / US | [N/P] |
| Former [2001/13] | For all designated states Hewlett-Packard Company, A Delaware Corporation 3000 Hanover Street Palo Alto, CA 94304 / US | ||
| Former [1999/23] | For all designated states Hewlett-Packard Company 3000 Hanover Street Palo Alto, California 94304 / US | Inventor(s) | 01 /
Naffziger, Samuel D. 3749 Ashmount Dr. Fort Collins, CO 80525 / US | [1999/23] | Representative(s) | Schoppe, Fritz, et al Schoppe, Zimmermann, Stöckeler & Zinkler Patentanwälte Postfach 246 82043 Pullach bei München / DE | [N/P] |
| Former [1999/23] | Schoppe, Fritz, Dipl.-Ing., et al Schoppe & Zimmermann Patentanwälte Postfach 71 08 67 81458 München / DE | Application number, filing date | 98108914.7 | 15.05.1998 | [1999/23] | Priority number, date | US19970955729 | 22.10.1997 Original published format: US 955729 | [1999/23] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0921639 | Date: | 09.06.1999 | Language: | EN | [1999/23] | Type: | B1 Patent specification | No.: | EP0921639 | Date: | 27.07.2005 | Language: | EN | [2005/30] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 23.04.1999 | Classification | IPC: | H03K19/096, H03K19/017 | [1999/23] | CPC: |
H03K19/0963 (EP,US)
| Designated contracting states | DE, FR, GB [2000/08] |
| Former [1999/23] | AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE | Title | German: | Dynamische logische Schaltung mit beschränktem Synchronisierungsbedarf und gespeichertem Ausgangszustand | [1999/23] | English: | Dynamic logic gate with relaxed timing requirements and output state holding | [1999/23] | French: | Circuit logique dynamique à encombrements réduits synchronisation avant état de sortie verrouillée | [2005/01] |
| Former [1999/23] | Circuit logique dynamique à encombrements réduits synchronisation avant état desortie verrouillée | Examination procedure | 17.08.1999 | Amendment by applicant (claims and/or description) | 17.08.1999 | Examination requested [1999/41] | 06.02.2004 | Despatch of a communication from the examining division (Time limit: M06) | 13.07.2004 | Reply to a communication from the examining division | 03.12.2004 | Communication of intention to grant the patent | 05.04.2005 | Fee for grant paid | 05.04.2005 | Fee for publishing/printing paid | Opposition(s) | 28.04.2006 | No opposition filed within time limit [2006/27] | Fees paid | Renewal fee | 25.04.2000 | Renewal fee patent year 03 | 20.04.2001 | Renewal fee patent year 04 | 21.05.2002 | Renewal fee patent year 05 | 26.05.2003 | Renewal fee patent year 06 | 24.05.2004 | Renewal fee patent year 07 | 19.05.2005 | Renewal fee patent year 08 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]WO9508872 (APPLE COMPUTER [US]) [A] 1-9* the whole document *; | [X]US5440243 (LYON RICHARD F [US]) [X] 1-6 * column 7, line 40 - column 8, line 10 *; | [X]US5550487 (LYON RICHARD F [US]) [X] 1-6 * claim 1 *; | [X]US5557620 (MILLER JR ROBERT H [US], et al) [X] 1-6 * column 7, line 19 - column 7, line 53; figures 3B,3D * |