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Extract from the Register of European Patents

EP About this file: EP0909033

EP0909033 - Rectifying transfer gate circuit [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  31.12.2004
Database last updated on 05.10.2024
Most recent event   Tooltip31.12.2004No opposition filed within time limitpublished on 16.02.2005  [2005/07]
Applicant(s)For all designated states
Samsung Electronics Co., Ltd.
416, Maetan-dong
Paldal-gu
Suwon-City, Kyungki-do / KR
[N/P]
Former [1999/15]For all designated states
Samsung Electronics Co., Ltd.
416, Maetan-dong, Paldal-gu
Suwon-city, Kyungki-do / KR
Inventor(s)01 / Makashima, Takashi
305-1405 Hyundae Apt., Kwangiang-dong
Seongdong-gu, Seoul / KR
[1999/15]
Representative(s)Musker, David Charles, et al
RGC Jenkins & Co.
26 Caxton Street
London SW1H 0RJ / GB
[N/P]
Former [1999/15]Musker, David Charles, et al
R.G.C. Jenkins & Co. 26 Caxton Street
London SW1H 0RJ / GB
Application number, filing date98203709.530.12.1993
[1999/15]
Priority number, dateKR1992002712331.12.1992         Original published format: KR 9227123
[1999/15]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0909033
Date:14.04.1999
Language:EN
[1999/15]
Type: A3 Search report 
No.:EP0909033
Date:20.10.1999
[1999/42]
Type: B1 Patent specification 
No.:EP0909033
Date:25.02.2004
Language:EN
[2004/09]
Search report(s)(Supplementary) European search report - dispatched on:EP02.09.1999
ClassificationIPC:H03K19/094
[1999/15]
CPC:
G06F7/501 (EP,US); H03K19/00 (KR); H01L27/0727 (EP,US);
H03K19/09441 (EP,US); H03K19/215 (EP,US); G06F2207/3876 (EP,US)
Designated contracting statesDE,   FR,   NL,   PT [1999/15]
TitleGerman:Gleichrichtende Übertragungstorschaltung[1999/15]
English:Rectifying transfer gate circuit[1999/15]
French:Circuit porte de transfert redresseuse[1999/15]
Examination procedure07.04.2000Examination requested  [2000/35]
16.07.2002Despatch of a communication from the examining division (Time limit: M04)
19.11.2002Reply to a communication from the examining division
04.06.2003Communication of intention to grant the patent
05.12.2003Fee for grant paid
05.12.2003Fee for publishing/printing paid
Parent application(s)   TooltipEP93310618.9  / EP0605253
Opposition(s)26.11.2004No opposition filed within time limit [2005/07]
Fees paidRenewal fee
26.11.1998Renewal fee patent year 03
26.11.1998Renewal fee patent year 04
26.11.1998Renewal fee patent year 05
26.11.1998Renewal fee patent year 06
09.12.1999Renewal fee patent year 07
13.12.2000Renewal fee patent year 08
20.12.2001Renewal fee patent year 09
12.12.2002Renewal fee patent year 10
12.12.2003Renewal fee patent year 11
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Documents cited:Search[A]US4801983  (UENO MASAHIRO [JP], et al) [A] 1-3 * column 3, line 3 - column 4, line 12; figure 1 * * column 11, line 28 - column 12, line 8; figures 5A,7A *;
 [A]US3879640  (SCHADE JR OTTO HEINRICH) [A] 1-3 * column 2, line 39 - column 4, line 6; figures 2,3 *;
 [A]EP0292782  (NISSAN MOTOR [JP]) [A] 1-3 * column 4, line 47 - column 6, line 1; figures 1,2 *;
 [XY]DE3441306  (SIEMENS AG [DE]) [X] 4-6 * page 4, line 26 - page 7, line 20 * [Y] 7,8;
 [A]EP0097574  (ITT [US], et al);
 [A]US4749887  (SANWO IKUO J [US], et al)
 [Y]  - "signal equivalence gate", IBM TECHNICAL DISCLOSURE BULLETIN, new york, (19850301), vol. 27, no. 10b, pages 6314 - 6315, XP002113115 [Y] 7,8 * page 6315, line 7 - line 13; figure 3 *
 [A]  - LEE, "low device count clocked cmos exclusive or circuit", IBM TECHNICAL DISCLOSURE BULLETIN, new york, (19850101), vol. 27, no. 8, page 4749, XP002113116
 [A]  - J. HILBEITEL, "cmos xor", IBM TECHNICAL DISCLOSURE BULLETIN, new york, (19840901), vol. 27, no. 4b, page 2639, XP002113117
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.