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EP0892275
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EP About this file: EP0892275
| EP0892275 - Method and apparatus for testing semiconductor and integrated circuit structures [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 28.06.2003 Database last updated on 18.03.2026 | Most recent event Tooltip | 11.07.2008 | Change - representative | published on 13.08.2008 [2008/33] | Applicant(s) | For all designated states SCHLUMBERGER TECHNOLOGIES, INC. 1601 Technology Drive San Jose California 95110-1397 / US | [N/P] |
| Former [1999/03] | For all designated states SCHLUMBERGER TECHNOLOGIES, INC. 1601 Technology Drive San Jose, California 95110-1397 / US | Inventor(s) | 01 /
Lo, Chiwoei Wayne 2039 Orestes Way Campbell, California 95008 / US | 02 /
Stoops, Mariel 613 Los Olivos Avenue Santa Clara, California 94062 / US | 03 /
Talbot, Christopher Graham 6 Summit Court Redwood City, California 94062 / US | [1999/03] | Representative(s) | Lemoyne, Didier Schlumberger Industries Propriété Intellectuelle 50 Avenue Jean Jaurès BP 620-04 92542 Montrouge Cedex / FR | [N/P] |
| Former [2008/33] | Lemoyne, Didier Schlumberger Industries Propriété Intellectuelle 50 Avenue Jean Jaurès BP 620-04 92542 Montrouge Cedex / FR | ||
| Former [1999/03] | Lemoyne, Didier Schlumberger Industries, Test & Transactions, BP 620-04 92542 Montrouge-Cedex / FR | Application number, filing date | 98401754.1 | 09.07.1998 | [1999/03] | Priority number, date | US19970892734 | 15.07.1997 Original published format: US 892734 | [1999/03] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0892275 | Date: | 20.01.1999 | Language: | EN | [1999/03] | Type: | A3 Search report | No.: | EP0892275 | Date: | 28.07.1999 | [1999/30] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 11.06.1999 | Classification | IPC: | G01R31/307, H01L21/66 | [1999/30] | CPC: |
G01R31/307 (EP,KR,US)
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| Former IPC [1999/03] | G01R31/307 | Designated contracting states | DE, FR, GB, IT, NL [2000/14] |
| Former [1999/03] | AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE | Title | German: | Verfahren und Gerät zur Prüfung von Strukturen auf Halbleitern und auf integrierten Schaltungen | [1999/03] | English: | Method and apparatus for testing semiconductor and integrated circuit structures | [1999/03] | French: | Procédé et appareil pour tester des structures sur des semiconducteurs et sur des circuits integrés | [1999/03] | Examination procedure | 03.09.1999 | Examination requested [1999/44] | 01.02.2003 | Application deemed to be withdrawn, date of legal effect [2003/33] | 17.03.2003 | Despatch of communication that the application is deemed to be withdrawn, reason: renewal fee not paid in time [2003/33] | Fees paid | Renewal fee | 24.06.2000 | Renewal fee patent year 03 | 12.07.2001 | Renewal fee patent year 04 | Penalty fee | Additional fee for renewal fee | 31.07.2002 | 05 M06 Not yet paid |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [XA] JPS60136235 [X] 1-6,8,10,11,13,14,19-24,26-28,34,37,38,42,53-58,60,61 * column 4, line 25 - column 10, line 30; figure 1 * * column 12, line 1 - line 15 * * column 12, line 35 - line 37 *[A] 59 | [X] JPS5979544 | [XA] PATENT ABSTRACTS OF JAPAN vol. 009, no. 295 (E - 360) 21 November 1985 (1985-11-21) [X] 1-6,8,10,11,13,14,19-24,26-28,34,37,38,42,53-58,60,61 * column 4, line 25 - column 10, line 30; figure 1 * * column 12, line 1 - line 15 * * column 12, line 35 - line 37 *[A] 59 | [X] PATENT ABSTRACTS OF JAPAN vol. 008, no. 190 (E - 263) 31 August 1984 (1984-08-31) [X] 42,46 * abstract * |