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EP0957515
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EP About this file: EP0957515
| EP0957515 - Method for manufacturing an SOI wafer [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 08.04.2005 Database last updated on 05.10.2024 | Most recent event Tooltip | 08.04.2005 | Application deemed to be withdrawn | published on 25.05.2005 [2005/21] | Applicant(s) | For all designated states STMicroelectronics Srl Via C. Olivetti, 2 20041 Agrate Brianza (Milano) / IT | [N/P] |
| Former [1999/46] | For all designated states STMicroelectronics S.r.l. Via C. Olivetti, 2 20041 Agrate Brianza (Milano) / IT | Inventor(s) | 01 /
Barlocchi, Gabriele Via Lucernate, 8 20010 Cornaredo / IT | 02 /
Villa, Flavio Francesco Via P. Lambertenghi, 23 20159 Milano / IT | [1999/46] | Representative(s) | Cerbaro, Elena, et al Studio Torta S.p.A. Via Viotti, 9 10121 Torino / IT | [N/P] |
| Former [1999/46] | Cerbaro, Elena, Dr., et al STUDIO TORTA S.r.l., Via Viotti, 9 10121 Torino / IT | Application number, filing date | 98830299.8 | 15.05.1998 | [1999/46] | Filing language | IT | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0957515 | Date: | 17.11.1999 | Language: | EN | [1999/46] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 21.10.1998 | Classification | IPC: | H01L21/762 | [1999/46] | CPC: |
H01L21/7624 (EP,US);
H01L21/76224 (EP,US);
H01L21/76264 (EP,US);
H01L21/7627 (EP,US);
H01L21/76283 (EP,US)
| Designated contracting states | DE, FR, GB, IT [2000/30] |
| Former [1999/46] | AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE | Title | German: | Herstellungsverfahren für eine Silizium-auf-einem-Isolator-(SOI)Halbleiterscheibe | [1999/46] | English: | Method for manufacturing an SOI wafer | [1999/46] | French: | Procédé de fabrication pour une plaquette de silicium à silicium sur isolant (SOI) | [1999/46] | Examination procedure | 15.05.2000 | Examination requested [2000/28] | 12.12.2003 | Despatch of a communication from the examining division (Time limit: M06) | 09.06.2004 | Reply to a communication from the examining division | 07.07.2004 | Despatch of a communication from the examining division (Time limit: M02) | 18.09.2004 | Application deemed to be withdrawn, date of legal effect [2005/21] | 22.12.2004 | Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time [2005/21] | Fees paid | Renewal fee | 18.05.2000 | Renewal fee patent year 03 | 17.05.2001 | Renewal fee patent year 04 | 28.05.2002 | Renewal fee patent year 05 | 26.05.2003 | Renewal fee patent year 06 | 26.05.2004 | Renewal fee patent year 07 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [XA]EP0223694 (FAIRCHILD SEMICONDUCTOR [US]) [X] 1,6,7,9 * the whole document * [A] 3,4,8; | [A]GB2156149 (PHILIPS ELECTRONIC ASSOCIATED) [A] 9 * page 3, column 1, line 2 - page 4, column 1, line 8; figures 2-5 * [A] ; | [XA]EP0226091 (TEXAS INSTRUMENTS INC [US]) [X] 9 * the whole document * [A] 1-8; | [XA]US4910165 (LEE STEVEN S [US], et al) [X] 9 * the whole document * [A] 1-8 | [A] - E.J. ZORINSKY, D.B. SPRATT, R.L. VIRKUS, "THE "ISLANDS" METHOD - A MANUFACTURABLE POROUS SILICON SOI TECHNOLOGY", IEDM 86 -TECHNICAL DIGEST, LOS ANGELES, CA, (19861207), pages 431 - 434, XP002079454 [A] 1-5,9 * the whole document * |