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EP0998756
European procedure
Extract from the Register of European Patents
EP About this file: EP0998756
| EP0998756 - DEVICE AND METHOD FOR PRODUCING A CHIP-SUBSTRATE CONNECTION [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 19.05.2006 Database last updated on 14.09.2024 | Most recent event Tooltip | 19.05.2006 | No opposition filed within time limit | published on 21.06.2006 [2006/25] | Applicant(s) | For all designated states Infineon Technologies AG St.-Martin-Strasse 53 81669 München / DE | [2005/28] |
| Former [2000/19] | For all designated states Infineon Technologies AG St.-Martin-Strasse 53 81541 München / DE | Inventor(s) | 01 /
GRÖTSCH, Stefan Von-Reiner-Strasse 1 D-93053 Regensburg / DE | 02 /
ALTHAUS, Hans-Ludwig Georgstrasse 12 D-93138 Lappersdorf / DE | 03 /
SPÄTH, Werner Burgstallerstrasse 10 D-83607 Holzkirchen / DE | 04 /
BOGNER, Georg Am Sandbügel 12 D-93138 Hainsacker / DE | [2000/19] | Representative(s) | Müller, Wolfram Hubertus, et al Patentanwälte Maikowski & Ninnemann Postfach 15 09 20 10671 Berlin / DE | [N/P] |
| Former [2001/33] | Müller, Wolfram Hubertus, Dipl.-Phys., et al Patentanwälte Maikowski & Ninnemann, Kurfürstendamm 54-55 10707 Berlin / DE | ||
| Former [2000/19] | Zedlitz, Peter, et al Patentanwalt, Postfach 22 13 17 80503 München / DE | Application number, filing date | 98947310.3 | 20.07.1998 | [2000/19] | WO1998DE02027 | Priority number, date | DE1997131740 | 23.07.1997 Original published format: DE 19731740 | [2000/19] | Filing language | DE | Procedural language | DE | Publication | Type: | A1 Application with search report | No.: | WO9905719 | Date: | 04.02.1999 | Language: | DE | [1999/05] | Type: | A1 Application with search report | No.: | EP0998756 | Date: | 10.05.2000 | Language: | DE | The application published by WIPO in one of the EPO official languages on 04.02.1999 takes the place of the publication of the European patent application. | [2000/19] | Type: | B1 Patent specification | No.: | EP0998756 | Date: | 13.07.2005 | Language: | DE | [2005/28] | Search report(s) | International search report - published on: | EP | 04.02.1999 | Classification | IPC: | H01L21/60 | [2000/19] | CPC: |
H01L24/75 (EP,US);
H01L21/60 (KR);
H01L24/83 (EP,US);
H01L2224/83224 (EP,US);
H01L2924/01006 (EP,US);
H01L2924/01013 (EP,US);
H01L2924/01019 (EP,US);
H01L2924/01024 (EP,US);
H01L2924/01033 (EP,US);
H01L2924/01047 (EP,US);
H01L2924/01057 (EP,US);
H01L2924/01068 (EP,US);
H01L2924/01077 (EP,US);
H01L2924/01078 (EP,US);
H01L2924/01079 (EP,US);
H01L2924/01082 (EP,US);
H01L2924/01322 (EP,US);
H01L2924/014 (EP,US);
H01L2924/12042 (EP,US);
H01L2924/14 (EP,US);
H05K3/3436 (EP,US);
H05K3/3494 (EP,US)
(-)
| C-Set: |
H01L2924/12042, H01L2924/00 (US,EP);
H01L2924/3512, H01L2924/00 (EP,US) | Designated contracting states | DE, FR, GB [2000/19] | Title | German: | VORRICHTUNG UND VERFAHREN ZUR HERSTELLUNG EINER CHIP-SUBSTRAT-VERBINDUNG | [2000/19] | English: | DEVICE AND METHOD FOR PRODUCING A CHIP-SUBSTRATE CONNECTION | [2000/19] | French: | PROCEDE ET DISPOSITIF POUR LA REALISATION D'UN ASSEMBLAGE PUCE-SUBSTRAT | [2000/19] | Entry into regional phase | 21.01.2000 | National basic fee paid | 21.01.2000 | Designation fee(s) paid | 21.01.2000 | Examination fee paid | Examination procedure | 05.01.1999 | Request for preliminary examination filed International Preliminary Examining Authority: EP | 21.01.2000 | Examination requested [2000/19] | 09.05.2003 | Despatch of a communication from the examining division (Time limit: M06) | 13.11.2003 | Reply to a communication from the examining division | 24.01.2005 | Communication of intention to grant the patent | 27.04.2005 | Fee for grant paid | 27.04.2005 | Fee for publishing/printing paid | Opposition(s) | 18.04.2006 | No opposition filed within time limit [2006/25] | Fees paid | Renewal fee | 17.07.2000 | Renewal fee patent year 03 | 04.07.2001 | Renewal fee patent year 04 | 01.07.2002 | Renewal fee patent year 05 | 01.07.2003 | Renewal fee patent year 06 | 08.07.2004 | Renewal fee patent year 07 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Cited in | International search | [XA]GB2244374 (STC PLC [GB]) [X] 1,2,10,11 * figure 1; claims 1,2 * [A] 3,4,12,13; | [A] - C.KARWATOWSKI ET AL., "Inspection for quartz insulation on laser-weldable metal layers in semiconductor device", IBM TECHNICAL DISCLOSURE BULLETIN, New York, (198201), vol. 24, no. 8, page 4286, XP002086307 [A] 4,5,13,14 * the whole document * | [A] - B.C.HENRY ET AL., "Semiconductor structure with infrared energy absorption layer", IBM TECHNICAL DISCLOSURE BULLETIN, New York, (190907), vol. 22, no. 2, page 681, XP002086308 [A] 2,6,7,11,15,16 * the whole document * | Examination | US4954453 |