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EP1119910
European procedure
Extract from the Register of European Patents
EP About this file: EP1119910
| EP1119910 - AREA EFFICIENT REALIZATION OF COEFFICIENT ARCHITECTURE FOR BIT-SERIAL FIR, IIR FILTERS AND COMBINATIONAL/SEQUENTIAL LOGIC STRUCTURE WITH ZERO LATENCY CLOCK OUTPUT [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 19.11.2004 Database last updated on 03.08.2024 | Most recent event Tooltip | 19.11.2004 | No opposition filed within time limit | published on 05.01.2005 [2005/01] | Applicant(s) | For all designated states STMicroelectronics Pte Ltd. 28 Ang Mo Kio Industrial Park 2 Singapore 569508 / SG | For all designated states STMicroelectronics Limited Sector 16A, Institutional Area, Noida 201 301 Uttar Pradesh / IN | [2004/02] |
| Former [2001/31] | For all designated states STMicroelectronics Pte Ltd. 28 Ang Mo Kio Industrial Park 2 Singapore 2056 / SG | ||
| For all designated states STMicroelectronics Limited Sector 16A, Industrial Area, Noida 201 301 Uttar Pradesh / IN | Inventor(s) | 01 /
MALIK, Rakesh-STMicroelectronics Limited Sector 16A, Institutional Area,Noida 201 301 Uttar Pradesh / IN | 02 /
GOEL, Puneet 735, Sector 7B,Chandigarh 160 019 Punjab / IN | [2001/31] | Representative(s) | Cerbaro, Elena, et al Studio Torta S.p.A. Via Viotti, 9 10121 Torino / IT | [N/P] |
| Former [2001/31] | Cerbaro, Elena, Dr., et al STUDIO TORTA S.r.l., Via Viotti, 9 10121 Torino / IT | Application number, filing date | 98950602.7 | 13.10.1998 | [2001/31] | WO1998SG00082 | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | WO0022729 | Date: | 20.04.2000 | Language: | EN | [2000/16] | Type: | A1 Application with search report | No.: | EP1119910 | Date: | 01.08.2001 | Language: | EN | The application published by WIPO in one of the EPO official languages on 20.04.2000 takes the place of the publication of the European patent application. | [2001/31] | Type: | B1 Patent specification | No.: | EP1119910 | Date: | 14.01.2004 | Language: | EN | [2004/03] | Search report(s) | International search report - published on: | EP | 20.04.2000 | Classification | IPC: | H03H17/02 | [2001/31] | CPC: |
H03H17/0223 (EP,US);
H03H17/0225 (EP,US);
H03H17/0227 (EP,US);
H03H2218/08 (EP,US);
H03H2218/10 (EP,US)
| Designated contracting states | DE, FR, GB, IT [2001/31] | Title | German: | FLÄCHENEFFIZIENTE HERSTELLUNG VON KOEFFIZIENT-ARCHITEKTUR FÜR BIT-SERIELLE FIR, IIR FILTER UND KOMBINATORISCHE/SEQUENTIELLE LOGISCHE STRUKTUR OHNE LATENZ | [2001/31] | English: | AREA EFFICIENT REALIZATION OF COEFFICIENT ARCHITECTURE FOR BIT-SERIAL FIR, IIR FILTERS AND COMBINATIONAL/SEQUENTIAL LOGIC STRUCTURE WITH ZERO LATENCY CLOCK OUTPUT | [2001/31] | French: | REALISATION A RENDEMENT SURFACIQUE D'UNE ARCHITECTURE DE COEFFICIENTS POUR FILTRES EN SERIE PAR BIT, RIF, RII ET STRUCTURE LOGIQUE COMBINATOIRE/SEQUENTIELLE A SORTIE D'HORLOGE A RETARD NUL | [2001/31] | Entry into regional phase | 10.05.2001 | National basic fee paid | 10.05.2001 | Designation fee(s) paid | 10.05.2001 | Examination fee paid | Examination procedure | 25.04.2000 | Request for preliminary examination filed International Preliminary Examining Authority: EP | 11.05.2001 | Examination requested [2001/31] | 30.07.2001 | Despatch of a communication from the examining division (Time limit: M08) | 15.05.2002 | Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time | 08.07.2002 | Reply to a communication from the examining division | 22.05.2003 | Communication of intention to grant the patent | 23.09.2003 | Fee for grant paid | 23.09.2003 | Fee for publishing/printing paid | Opposition(s) | 15.10.2004 | No opposition filed within time limit [2005/01] | Request for further processing for: | 08.07.2002 | Request for further processing filed | 03.07.2002 | Full payment received (date of receipt of payment) Request granted | 22.07.2002 | Decision despatched | Fees paid | Renewal fee | 10.05.2001 | Renewal fee patent year 03 | 31.01.2002 | Renewal fee patent year 04 | 28.10.2002 | Renewal fee patent year 05 | 27.10.2003 | Renewal fee patent year 06 | Penalty fee | Additional fee for renewal fee | 31.10.2001 | 04 M06 Fee paid on 31.01.2002 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Cited in | International search | [A]WO9423493 (SARAMAEKI TAPIO [FI], et al) [A] 1 * page 6, line 10 - page 9, line 26 *; | [A] - DAWOOD ALAM ET AL, "VLSI IMPLEMENTATION OF A NEW BIT-LEVEL PIPELINED ARCHITECTURE FOR 2-D ALLPASS DIGITAL FILTERS", 1995 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), SEATTLE, APR. 30 - MAY 3, 1995, INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, (19950430), vol. 1, pages 724 - 727, XP000583315 [A] 1 * paragraph [00II] * * paragraph [0III] * | [A] - K. MANIVANNAN ET AL., "Minimal Multiplier Realization of 2-D All-Pass Digital Filters", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS., NEW YORK US, (198804), vol. 35, no. 4, pages 480 - 484, XP002104516 [A] 1 DOI: http://dx.doi.org/10.1109/31.1771 | Examination | - DUNCAN P. ET AL, "Strategies for Design Automation of High Speed Digital Filters", JOURNAL OF VLSI SIGNAL PROCESSING, DORDRECHT, NL, (1995), no. 9, pages 105 - 118 |