-
EP0973204
European procedure
Extract from the Register of European Patents
EP About this file: EP0973204
| EP0973204 - Method of manufacturing a MOS-Transistor device [Right-click to bookmark this link] | |||
| Former [2000/03] | MOS-Transistor with enhanced withstanding voltage and reduced on-resistance | ||
| [2005/33] | Status | No opposition filed within time limit Status updated on 05.01.2007 Database last updated on 10.05.2025 | Most recent event Tooltip | 05.01.2007 | No opposition filed within time limit | published on 07.02.2007 [2007/06] | Applicant(s) | For all designated states ELMOS Semiconductor AG Heinrich-Hertz-Strasse 1 44227 Dortmund / DE | [N/P] |
| Former [2000/03] | For all designated states ELMOS Semiconductor AG Heinrich-Hertz-Strasse 1 44227 Dortmund / DE | Inventor(s) | 01 /
Gehrmann, Andreas Verbindungsweg 18 44267 Dortmund / DE | 02 /
Bornefeld, Ralf Grünental 2 58579 Schalksmühle / DE | [2000/13] | Representative(s) | dompatent von Kreisler Selting Werner - Partnerschaft von Patent- und Rechtsanwälten mbB Deichmannhaus am Dom Bahnhofsvorplatz 1 50667 Köln / DE | [N/P] |
| Former [2000/03] | Hilleringmann, Jochen, Dipl.-Ing., et al Patentanwälte von Kreisler-Selting-Werner, Postfach 10 22 41 50462 Köln / DE | Application number, filing date | 99112270.6 | 25.06.1999 | [2000/03] | Priority number, date | DE1998128522 | 26.06.1998 Original published format: DE 19828522 | [2000/03] | Filing language | DE | Procedural language | DE | Publication | Type: | A2 Application without search report | No.: | EP0973204 | Date: | 19.01.2000 | Language: | DE | [2000/03] | Type: | A3 Search report | No.: | EP0973204 | Date: | 25.07.2001 | [2001/30] | Type: | B1 Patent specification | No.: | EP0973204 | Date: | 01.03.2006 | Language: | DE | [2006/09] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 12.06.2001 | Classification | IPC: | H01L29/78, H01L21/336, H01L21/266, H01L21/8234 | [2001/30] | CPC: |
H10D30/0221 (EP,US);
H10D30/603 (EP,US);
H10D62/151 (EP);
H10D84/013 (EP,US);
H10D84/038 (EP,US);
H10D84/83 (EP,US);
H10D64/516 (EP)
(-)
|
| Former IPC [2000/03] | H01L29/78 | Designated contracting states | AT, BE, CH, DE, FR, GB, IE, IT, LI, NL [2002/16] |
| Former [2000/03] | AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE | Title | German: | Verfahren zur Herstellung einer MOS-Transistoranordnung | [2005/33] | English: | Method of manufacturing a MOS-Transistor device | [2005/33] | French: | Procédé pour la fabrication d'un dispositif de transistor MOS | [2005/33] |
| Former [2000/03] | MOS-Transistor mit hoher Spannungsfestigkeit und niedrigem Einschaltwiderstand | ||
| Former [2000/03] | MOS-Transistor with enhanced withstanding voltage and reduced on-resistance | ||
| Former [2000/03] | Transistor MOS avec tension de claquage élevée et resistance passante reduite | Examination procedure | 24.08.2001 | Examination requested [2001/43] | 26.02.2002 | Loss of particular rights, legal effect: designated state(s) | 04.06.2002 | Despatch of communication of loss of particular rights: designated state(s) CY, DK, ES, FI, GR, LU, MC, PT, SE | 22.07.2002 | Despatch of a communication from the examining division (Time limit: M04) | 16.11.2002 | Reply to a communication from the examining division | 29.12.2003 | Despatch of a communication from the examining division (Time limit: M04) | 27.04.2004 | Reply to a communication from the examining division | 20.09.2004 | Despatch of a communication from the examining division (Time limit: M04) | 07.10.2004 | Reply to a communication from the examining division | 05.09.2005 | Communication of intention to grant the patent | 09.12.2005 | Fee for grant paid | 09.12.2005 | Fee for publishing/printing paid | Opposition(s) | 04.12.2006 | No opposition filed within time limit [2007/06] | Fees paid | Renewal fee | 26.06.2001 | Renewal fee patent year 03 | 25.06.2002 | Renewal fee patent year 04 | 27.06.2003 | Renewal fee patent year 05 | 26.06.2004 | Renewal fee patent year 06 | 28.06.2005 | Renewal fee patent year 07 | Penalty fee | Penalty fee Rule 85a EPC 1973 | 07.03.2002 | CY M01 Not yet paid | 07.03.2002 | DK M01 Not yet paid | 07.03.2002 | ES M01 Not yet paid | 07.03.2002 | FI M01 Not yet paid | 07.03.2002 | GR M01 Not yet paid | 07.03.2002 | LU M01 Not yet paid | 07.03.2002 | MC M01 Not yet paid | 07.03.2002 | PT M01 Not yet paid | 07.03.2002 | SE M01 Not yet paid |
| Opt-out from the exclusive Tooltip competence of the Unified Patent Court | See the Register of the Unified Patent Court for opt-out data | ||
| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]JPH0730107 ; | [DA]WO9713277 (EL MOS ELEKTRONIK IN MOS TECHN [DE], et al); | Examination | US5075242 |