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Extract from the Register of European Patents

EP About this file: EP0998175

EP0998175 - Method for soldering Dpak-type electronic components to circuit boards [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  12.12.2003
Database last updated on 21.09.2024
Most recent event   Tooltip22.04.2005Lapse of the patent in a contracting statepublished on 08.06.2005  [2005/23]
Applicant(s)For all designated states
FORD MOTOR COMPANY
The American Road
Dearborn, MI 48126 / US
[N/P]
Former [2000/18]For all designated states
Ford Motor Company
The American Road
Dearborn, MI 48126 / US
Inventor(s)01 / Sinkunas, Peter Joseph
7111, Foxcreek Drive
Canton, Michigan 48187 / US
[2000/18]
Representative(s)Messulam, Alec Moses, et al
Harrison IP Limited
3 Ebor House
London Ebor Business Park
Millfield Lane
Nether Poppleton York YO26 6QY / GB
[N/P]
Former [2000/18]Messulam, Alec Moses, et al
A. Messulam & Co. 24 Broadway
Leigh-on-Sea Essex SS9 1BN / GB
Application number, filing date99307378.217.09.1999
[2000/18]
Priority number, dateUS1998017204714.10.1998         Original published format: US 172047
[2000/18]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report 
No.:EP0998175
Date:03.05.2000
Language:EN
[2000/18]
Type: B1 Patent specification 
No.:EP0998175
Date:05.02.2003
Language:EN
[2003/06]
Search report(s)(Supplementary) European search report - dispatched on:EP31.01.2000
ClassificationIPC:H05K3/34
[2000/18]
CPC:
H05K3/341 (EP,US); H05K3/3494 (EP,US); H01L2224/05553 (EP,US);
H01L2224/48091 (EP,US); H01L2224/48247 (EP,US); H01L2224/48472 (EP,US);
H05K2201/10166 (EP,US); H05K2201/10969 (EP,US); H05K2203/0405 (EP,US);
H05K2203/107 (EP,US); Y02P70/50 (EP,US) (-)
C-Set:
H01L2224/48091, H01L2924/00014 (EP,US);
H01L2224/48472, H01L2224/48091, H01L2924/00 (US,EP);
H01L2224/48472, H01L2224/48247, H01L2924/00 (US,EP)
Designated contracting statesDE,   ES,   GB [2001/03]
Former [2000/18]AT,  BE,  CH,  CY,  DE,  DK,  ES,  FI,  FR,  GB,  GR,  IE,  IT,  LI,  LU,  MC,  NL,  PT,  SE 
TitleGerman:Verfahren zum Löten eines D-pak Bauteiles auf einer gedruckten Schaltungsplatte[2000/18]
English:Method for soldering Dpak-type electronic components to circuit boards[2000/18]
French:Procédé pour souder des composants électroniques du type D-pak sur une plaquette de circuit imprimé[2000/18]
Examination procedure12.10.2000Examination requested  [2000/49]
28.03.2002Despatch of communication of intention to grant (Approval: Yes)
13.08.2002Communication of intention to grant the patent
23.08.2002Fee for grant paid
23.08.2002Fee for publishing/printing paid
Opposition(s)06.11.2003No opposition filed within time limit [2004/05]
Fees paidRenewal fee
30.07.2001Renewal fee patent year 03
22.08.2002Renewal fee patent year 04
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipES18.09.2003
[2005/23]
Documents cited:Search[A]US5112635  (LIEBERMANN BENNO E [US]) [A] 1-7 * the whole document *;
 [A]JPS59150665
 [A]  - PATENT ABSTRACTS OF JAPAN, (19841221), vol. 008, no. 280, Database accession no. (M - 347), & JP59150665 A 19840828 (TOSHIBA KK) [A] 1-7 * abstract *
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.