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EP1005163
European procedure
Extract from the Register of European Patents
EP About this file: EP1005163
| EP1005163 - Programmable logic device architectures [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 14.09.2007 Database last updated on 31.08.2024 | Most recent event Tooltip | 25.07.2008 | Change - representative | published on 27.08.2008 [2008/35] | Applicant(s) | For all designated states ALTERA CORPORATION 101 Innovation Drive San Jose, CA 95134 / US | [N/P] |
| Former [2006/41] | For all designated states ALTERA CORPORATION 101 Innovation Drive San Jose California 95134 / US | ||
| Former [2000/22] | For all designated states Altera Corporation 101 Innovation Drive San Jose, California 95134 / US | Inventor(s) | 01 /
Jefferson, David E. Altera Corporation, 101 Innovation Drive San Jose, CA 95134 / US | 02 /
Lee, Andy L. Altera Corporation, 101 Innovation Drive San Jose, CA 95134 / US | 03 /
Lane, Christopher F. Altera Corporation, 101 Innovation Drive San Jose, CA 95134 / US | 04 /
McClintock, Cameron Altera Corporation, 101 Innovation Drive San Jose, CA 95134 / US | 05 /
Mejia, Manuel Altera Corporation, 101 Innovation Drive San Jose, CA 95134 / US | 06 /
Cliff, Richard G. Altera Corporation, 101 Innovation Drive San Jose, CA 95134 / US | 07 /
Schleicher, James Altera Corporation, 101 Innovation Drive San Jose, CA 95134 / US | 08 /
Pederson, Bruce B. Altera Corporation, 101 Innovation Drive San Jose, CA 95134 / US | 09 /
Reddy, Srinivas T. Altera Corporation, 101 Innovation Drive San Jose, CA 95134 / US | [2000/22] | Representative(s) | Hogg, Jeffery Keith, et al Withers & Rogers LLP Goldings House 2 Hays Lane London SE1 2HW / GB | [2008/35] |
| Former [2000/22] | Hogg, Jeffery Keith, et al Withers & Rogers, Goldings House, 2 Hays Lane London SE1 2HW / GB | Application number, filing date | 99309072.9 | 15.11.1999 | [2000/22] | Priority number, date | US19980109417P | 18.11.1998 Original published format: US 109417 P | US19990266235 | 10.03.1999 Original published format: US 266235 | [2000/22] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP1005163 | Date: | 31.05.2000 | Language: | EN | [2000/22] | Type: | A3 Search report | No.: | EP1005163 | Date: | 24.10.2001 | [2001/43] | Type: | B1 Patent specification | No.: | EP1005163 | Date: | 11.10.2006 | Language: | EN | [2006/41] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 06.09.2001 | Classification | IPC: | H03K19/177 | [2000/22] | CPC: |
H03K19/1776 (EP,US);
H03K19/17736 (EP,US)
| Designated contracting states | DE, FR, GB, IT, NL [2002/29] |
| Former [2000/22] | AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE | Title | German: | Architekturen für programmierbare logische Vorrichtungen | [2000/22] | English: | Programmable logic device architectures | [2000/22] | French: | Architectures de dispositifs logiques programmables | [2000/22] | Examination procedure | 07.01.2002 | Examination requested [2002/12] | 24.03.2005 | Despatch of a communication from the examining division (Time limit: M04) | 02.08.2005 | Reply to a communication from the examining division | 10.04.2006 | Communication of intention to grant the patent | 07.08.2006 | Fee for grant paid | 07.08.2006 | Fee for publishing/printing paid | Opposition(s) | 12.07.2007 | No opposition filed within time limit [2007/42] | Fees paid | Renewal fee | 07.11.2001 | Renewal fee patent year 03 | 07.11.2002 | Renewal fee patent year 04 | 07.11.2003 | Renewal fee patent year 05 | 08.11.2004 | Renewal fee patent year 06 | 07.11.2005 | Renewal fee patent year 07 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | IT | 11.10.2006 | [2008/17] | Documents cited: | Search | [A]EP0630115 (PILKINGTON MICRO ELECTRONICS [GB]) [A] 1 * column A *; | [A]US5455525 (HO WALFORD W [US], et al) [A] 1 * column A *; | [A]GB2305759 (PILKINGTON MICRO ELECTRONICS [GB]) [A] 1* column A *; | [X] - BURSKY D, "Variable-Grain Architecture Pumps UP FPGA Performance", ELECTRONIC DESIGN, PENTON PUBLISHING, CLEVELAND, OH, US, (19980223), vol. 46, no. 4, ISSN 0013-4872, page 102,104,106, XP002165019 [X] 1,4,13,18-20 * the whole document * |