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Extract from the Register of European Patents

EP About this file: EP0961318

EP0961318 - Integrated circuit with etch stop layer [Right-click to bookmark this link]
StatusThe application is deemed to be withdrawn
Status updated on  14.08.2009
Database last updated on 09.07.2024
Most recent event   Tooltip14.08.2009Application deemed to be withdrawnpublished on 16.09.2009  [2009/38]
Applicant(s)For all designated states
STMicroelectronics S.A.
29, Boulevard Romain Rolland
92120 Montrouge / FR
For:FR 
FRANCE TELECOM
6 Place d'Alleray
75015 Paris / FR
[N/P]
Former [2001/51]For all designated states
STMicroelectronics S.A.
29, Boulevard Romain Rolland
92120 Montrouge / FR
For:FR 
FRANCE TELECOM
6, Place d'Alleray
75015 Paris / FR
Former [1999/48]For all designated states
STMicroelectronics SA
7, avenue Gallieni
94250 Gentilly Cedex / FR
For:FR 
FRANCE TELECOM
6, Place d'Alleray
75015 Paris / FR
Inventor(s)01 / Gayet, Philippe
Rue de l'Eglise
38660 St. Vincent de Mercuze / FR
02 / Granger, Eric
Cidex 159A
38920 Crolles / FR
[1999/48]
Representative(s)Casalonga, Axel
Casalonga & Partners Bayerstrasse 73
80335 München / DE
[N/P]
Former [1999/48]Casalonga, Axel
BUREAU D.A. CASALONGA - JOSSE Morassistrasse 8
80469 München / DE
Application number, filing date99401205.219.05.1999
[1999/48]
Priority number, dateFR1998000668727.05.1998         Original published format: FR 9806687
[1999/48]
Filing languageFR
Procedural languageFR
PublicationType: A1 Application with search report 
No.:EP0961318
Date:01.12.1999
Language:FR
[1999/48]
Search report(s)(Supplementary) European search report - dispatched on:EP09.07.1999
ClassificationIPC:H01L21/768, H01L23/522
[1999/48]
CPC:
H01L23/5226 (EP,US); H01L21/76802 (EP); H01L21/76816 (US);
H01L21/76829 (EP); H01L2924/0002 (EP,US)
C-Set:
H01L2924/0002, H01L2924/00 (EP,US)
Designated contracting statesDE,   FR,   GB,   IT [2000/32]
Former [1999/48]AT,  BE,  CH,  CY,  DE,  DK,  ES,  FI,  FR,  GB,  GR,  IE,  IT,  LI,  LU,  MC,  NL,  PT,  SE 
TitleGerman:Integrierte Schaltung mit Ätzstopschicht[1999/48]
English:Integrated circuit with etch stop layer[1999/48]
French:Circuit intégré avec couche d'arrêt[1999/48]
Examination procedure07.12.1999Examination requested  [2000/05]
30.05.2006Despatch of a communication from the examining division (Time limit: M06)
09.10.2006Reply to a communication from the examining division
25.01.2007Despatch of a communication from the examining division (Time limit: M06)
11.05.2007Reply to a communication from the examining division
20.12.2007Despatch of a communication from the examining division (Time limit: M06)
16.06.2008Reply to a communication from the examining division
11.11.2008Despatch of a communication from the examining division (Time limit: M04)
24.03.2009Application deemed to be withdrawn, date of legal effect  [2009/38]
29.04.2009Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time  [2009/38]
Fees paidRenewal fee
25.04.2001Renewal fee patent year 03
24.05.2002Renewal fee patent year 04
13.05.2003Renewal fee patent year 05
13.05.2004Renewal fee patent year 06
12.05.2005Renewal fee patent year 07
23.03.2006Renewal fee patent year 08
29.05.2007Renewal fee patent year 09
29.05.2008Renewal fee patent year 10
Penalty fee
Additional fee for renewal fee
31.05.200911   M06   Not yet paid
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Documents cited:Search[A]JPH08241924  ;
 [A]US5110712  (KESSLER DANIEL D [US], et al) [A] * figures 2-4 *;
 [A]US5244837  (DENNISON CHARLES H [US]) [A] * figures 4,5,7-13 *;
 [A]US5451543  (WOO MICHAEL P [US], et al) [A] * figures 11,12 *;
 [A]US5598027  (MATSUURA MASAZUMI [JP]) [A] 1,8 * figures 5-9 *;
 [PX]US5817574  (GARDNER DONALD S [US]) [PX] 8 * figure 2 *
 [A]  - PATENT ABSTRACTS OF JAPAN, (19970131), vol. 097, no. 001, & JP08241924 A 19960917 (SONY CORP) [A] 1,8 * abstract *
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.