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EP0991113
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EP About this file: EP0991113
| EP0991113 - A process for fabricating a self-aligned T-shaped gate electrode with reduced resistivity [Right-click to bookmark this link] | |||
| Former [2000/14] | A process for fabricating a self-aligned T-shaped gate electrode with reduced resistivity | ||
| [2004/39] | Status | The application has been withdrawn Status updated on 12.10.2007 Database last updated on 11.01.2025 | Most recent event Tooltip | 12.10.2007 | Withdrawal of application | published on 14.11.2007 [2007/46] | Applicant(s) | For all designated states Chartered Semiconductor Manufacturing Pte Ltd. 60 Woodlands Industrial Estate Park D, Street 2 Singapore 738406 / SG | [N/P] |
| Former [2000/14] | For all designated states Chartered Semiconductor Manufacturing Pte Ltd. 60 Woodlands Industrial Estate Park D, Street 2 Singapore 738406 / SG | Inventor(s) | 01 /
Pan, Yang Blk IP, Pine Grove, no. 02,77, Singapore Singapore 591401 / SG | 02 /
Liu, Erzhuang Blk 236, 06-47, Chon Chu Kang Central, Singapore Singapore 680236 / SG | [2000/14] | Representative(s) | Schuffenecker, Thierry 120 Chemin de la Maure 06800 Cagnes-sur-Mer / FR | [N/P] |
| Former [2005/49] | Schuffenecker, Thierry 120 Chemin de la Maure 06800 Cagnes sur Mer / FR | ||
| Former [2000/14] | Schuffenecker, Thierry 97, chemin de Cassiopée, Domaine de l'étoile 06610 La Gaude / FR | Application number, filing date | 99480094.4 | 30.09.1999 | [2000/14] | Priority number, date | US19980165004 | 01.10.1998 Original published format: US 165004 | [2000/14] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0991113 | Date: | 05.04.2000 | Language: | EN | [2000/14] | Type: | A3 Search report | No.: | EP0991113 | Date: | 22.09.2004 | [2004/39] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 09.08.2004 | Classification | IPC: | H01L21/28, H01L21/338 | [2000/14] | CPC: |
H10D30/0225 (EP,US);
H01L21/28114 (EP,US);
H10D30/601 (EP,US);
H10D64/018 (EP);
H10D64/518 (EP,US);
H10D30/0212 (EP,US)
| Designated contracting states | AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE [2000/14] | Title | German: | Verfahren zur Herstellung einer T-förmigen Gate-Elektrode mit geringer Wiederstand | [2000/14] | English: | A process for fabricating a self-aligned T-shaped gate electrode with reduced resistivity | [2004/39] | French: | Procédé de fabrication d'une grille en forme de T auto-alignée à résistivité réduite | [2000/14] |
| Former [2000/14] | A process for fabricating a self-aligned T-shaped gate electrode with reduced resistivity | Examination procedure | 22.03.2005 | Examination requested [2005/20] | 07.10.2007 | Application withdrawn by applicant [2007/46] | Fees paid | Renewal fee | 30.09.2002 | Renewal fee patent year 04 | 18.10.2003 | Renewal fee patent year 05 | 27.09.2004 | Renewal fee patent year 06 | 29.09.2005 | Renewal fee patent year 07 | 30.09.2006 | Renewal fee patent year 08 | Penalty fee | Additional fee for renewal fee | 27.11.2001 | 03 M06 Fee paid on 13.02.2002 | 30.09.2003 | 05 M06 Fee paid on 18.10.2003 |
| Opt-out from the exclusive Tooltip competence of the Unified Patent Court | See the Register of the Unified Patent Court for opt-out data | ||
| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]US5405787 (KURIMOTO KAZUMI [JP]); | [DA]US5498560 (SHARMA UMESH [US], et al); | [A]EP0777268 (LUCENT TECHNOLOGIES INC [US]); | [DA]US5658826 (CHUNG KI WOONG [KR]); | [DA]US5731239 (WONG HARIANTO [SG], et al) |