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EP About this file: EP1101247

EP1101247 - METHOD OF PRODUCING AN INTERCONNECT STRUCTURE FOR AN INTEGRATED CIRCUIT [Right-click to bookmark this link]
Status	No opposition filed within time limit Status updated on 14.09.2007 Database last updated on 05.10.2024
Most recent event Tooltip	08.01.2010	Lapse of the patent in a contracting state State(s) deleted from list of lapses: ES, FR	published on 10.02.2010 [2010/06]
Applicant(s)	For all designated states Applied Materials, Inc. 3050 Bowers Avenue Santa Clara, CA 95054 / US
	[N/P]
Former [2006/45]	For all designated states APPLIED MATERIALS, INC. 3050 Bowers Avenue Santa Clara, California 95054 / US
Former [2001/21]	For all designated states Applied Materials, Inc. 3050 Bowers Avenue Santa Clara, California 95054 / US
Inventor(s)	01 / NAIK, Mehul 3088 Valleywood Court San Jose, CA 95148 / US
	02 / BROYDO, Samuel 26496 Purissima Road Los Altos Hills, CA 94022 / US
	[2001/27]
Former [2001/21]	01 / NAIK, Mehul 1608 LaRossa Circle San Jose, CA 95125 / US
	02 / BROYDO, Samuel 26496 Purissima Road Los Altos Hills, CA 94022 / US
Representative(s)	Bayliss, Geoffrey Cyril, et al BOULT WADE TENNANT Verulam Gardens 70 Gray's Inn Road London WC1X 8BT / GB
	[N/P]
Former [2001/21]	Bayliss, Geoffrey Cyril, et al BOULT WADE TENNANT, Verulam Gardens 70 Gray's Inn Road London WC1X 8BT / GB
Application number, filing date	99932210.0	01.07.1999
	[2001/21]
	WO1999US15073
Priority number, date	US19980122080	23.07.1998 Original published format: US 122080
	[2001/21]
Filing language	EN
Procedural language	EN
Publication	Type:	A1 Application with search report
	No.:	WO0005763
	Date:	03.02.2000
	Language:	EN
	[2000/05]
	Type:	A1 Application with search report
	No.:	EP1101247
	Date:	23.05.2001
	Language:	EN
	The application published by WIPO in one of the EPO official languages on 03.02.2000 takes the place of the publication of the European patent application.
	[2001/21]
	Type:	B1 Patent specification
	No.:	EP1101247
	Date:	08.11.2006
	Language:	EN
	[2006/45]
Search report(s)	International search report - published on:	EP	03.02.2000
Classification	IPC:	H01L21/768	[2001/21]
	CPC:	H01L21/76808 (EP,US); H01L21/768 (KR)
Designated contracting states	BE, CH, DE, GB, LI, NL [2006/45]
Former [2001/21]	AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE
Title	German:	VERFAHREN ZUR HERSTELLUNG EINER LEITERBAHNSTRUKTUR FÜR EINE INTEGRIERTE SCHALTUNG	[2001/21]
	English:	METHOD OF PRODUCING AN INTERCONNECT STRUCTURE FOR AN INTEGRATED CIRCUIT	[2001/21]
	French:	PROCEDE RELATIF A L'ELABORATION D'UNE STRUCTURE D'INTERCONNEXION POUR CIRCUIT INTEGRE	[2001/21]
Entry into regional phase	07.02.2001	National basic fee paid
	07.02.2001	Designation fee(s) paid
	07.02.2001	Examination fee paid
Examination procedure	09.02.2000	Request for preliminary examination filed International Preliminary Examining Authority: EP
	07.02.2001	Examination requested [2001/21]
	29.05.2006	Communication of intention to grant the patent
	22.09.2006	Fee for grant paid
	22.09.2006	Fee for publishing/printing paid
Opposition(s)	09.08.2007	No opposition filed within time limit [2007/42]
Fees paid	Renewal fee
	10.08.2001	Renewal fee patent year 03
	21.06.2002	Renewal fee patent year 04
	04.07.2003	Renewal fee patent year 05
	09.07.2004	Renewal fee patent year 06
	08.07.2005	Renewal fee patent year 07
	10.07.2006	Renewal fee patent year 08
	Penalty fee
	Additional fee for renewal fee
	31.07.2001	03 M03 Fee paid on 10.08.2001
Opt-out from the exclusive Tooltip competence of the Unified Patent Court	See the Register of the Unified Patent Court for opt-out data
	Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition Tooltip	BE	08.11.2006
	CH	08.11.2006
	LI	08.11.2006
	NL	08.11.2006
	[2010/06]
Former [2009/30]	BE	08.11.2006
	CH	08.11.2006
	LI	08.11.2006
	NL	08.11.2006
	ES	31.07.2007
	FR	31.07.2007
Former [2007/31]	BE	08.11.2006
	CH	08.11.2006
	LI	08.11.2006
	NL	08.11.2006
Cited in	International search	[A]EP0435187 (FUJITSU LTD [JP]) [A] 1-17 * column 19, line 35 - column 20, line 58 * * column 21, line 46 - line 53; figure 8 *;
		[XA]WO9710612 (ADVANCED MICRO DEVICES INC [US]) [X] 1-3,5-8 * page 11, line 36 - page 12, line 4 * * page 12, line 31 - page 13, line 21 * * page 15, line 25 - page 16, line 8; figure 3 * [A] 9-12,15-17;
		[A]US5693568 (LIU YOWJUANG W [US], et al) [A] 1-17* column 6, line 39 - column 7, line 51; figures 2-4 *;
		[A]US5702982 (LEE CHUNG-KUANG [TW], et al) [A] 4,13 * column 5, line 21 - line 67; figures 2,3 *;
		[X]EP0843348 (APPLIED MATERIALS INC [US]) [X] 18,21 * the whole document *

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