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Extract from the Register of European Patents

EP About this file: EP1316092

EP1316092 - CIRCUIT AND METHOD FOR MULTI-PHASE ALIGNMENT [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  20.05.2011
Database last updated on 17.05.2024
Most recent event   Tooltip19.10.2012Lapse of the patent in a contracting state
New state(s): TR		published on 21.11.2012  [2012/47]
Applicant(s)For all designated states
Broadcom Corporation
5300 California Avenue
Irvine, CA 92617 / US
[2007/21]
Former [2003/23]For all designated states
Broadcom Corporation
16215 Alton Parkway
Irvine, California 92618 / US
Inventor(s)01 / SINGOR, Frank, W.
2830 Park Place
Laguna Beach, CA 92651 / US
 [2003/23]
Representative(s)Jehle, Volker Armin, et al
Bosch Jehle Patentanwaltsgesellschaft mbH
Flüggenstrasse 13
80639 München / DE
[N/P]
Former [2008/52]Jehle, Volker Armin, et al
Bosch Jehle Patentanwaltsgesellschaft mbH Flüggenstrasse 13
80639 München / DE
Former [2003/23]Jehle, Volker Armin
Patentanwälte Bosch, Graf von Stosch, Jehle, Flüggenstrasse 13
80639 München / DE
Application number, filing date01959871.303.08.2001
[2003/23]
WO2001US41533
Priority number, dateUS20000223112P03.08.2000         Original published format: US 223112 P
US20000224169P09.08.2000         Original published format: US 224169 P
[2003/23]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report
No.:WO0213201
Date:14.02.2002
Language:EN
[2002/07]
Type: A2 Application without search report 
No.:EP1316092
Date:04.06.2003
Language:EN
The application published by WIPO in one of the EPO official languages on 14.02.2002 takes the place of the publication of the European patent application.
[2003/23]
Type: B1 Patent specification 
No.:EP1316092
Date:14.07.2010
Language:EN
[2010/28]
Search report(s)International search report - published on:EP10.05.2002
ClassificationIPC:G11C27/02, G06F1/06, H03K5/15
[2003/23]
CPC:
H03K5/15 (EP,US); G06F1/08 (EP,US); G11C27/024 (EP,US)
Designated contracting statesAT,   BE,   CH,   CY,   DE,   DK,   ES,   FI,   FR,   GB,   GR,   IE,   IT,   LI,   LU,   MC,   NL,   PT,   SE,   TR [2003/23]
TitleGerman:SCHALTUNG UND VERFAHREN FÜR MULTIPHASENANPASSUNG[2003/23]
English:CIRCUIT AND METHOD FOR MULTI-PHASE ALIGNMENT[2003/23]
French:CIRCUIT ET PROCEDE D'ALIGNEMENT MULTIPHASE[2003/23]
Entry into regional phase03.03.2003National basic fee paid 
03.03.2003Designation fee(s) paid 
03.03.2003Examination fee paid 
Examination procedure27.02.2002Request for preliminary examination filed
International Preliminary Examining Authority: EP
03.03.2003Examination requested  [2003/23]
20.12.2007Despatch of a communication from the examining division (Time limit: M06)
05.06.2008Reply to a communication from the examining division
19.06.2008Despatch of a communication from the examining division (Time limit: M04)
25.08.2008Reply to a communication from the examining division
08.09.2008Despatch of a communication from the examining division (Time limit: M06)
17.02.2009Reply to a communication from the examining division
03.03.2009Despatch of a communication from the examining division (Time limit: M04)
05.05.2009Reply to a communication from the examining division
28.05.2009Despatch of a communication from the examining division (Time limit: M04)
31.07.2009Reply to a communication from the examining division
20.08.2009Despatch of a communication from the examining division (Time limit: M04)
21.12.2009Reply to a communication from the examining division
04.02.2010Communication of intention to grant the patent
02.06.2010Fee for grant paid
02.06.2010Fee for publishing/printing paid
Opposition(s)15.04.2011No opposition filed within time limit [2011/25]
Fees paidRenewal fee
06.08.2003Renewal fee patent year 03
31.08.2004Renewal fee patent year 04
31.08.2005Renewal fee patent year 05
31.08.2006Renewal fee patent year 06
31.08.2007Renewal fee patent year 07
01.09.2008Renewal fee patent year 08
31.08.2009Renewal fee patent year 09
Opt-out from the exclusive  Tooltip
competence of the Unified
Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipAT14.07.2010
BE14.07.2010
CY14.07.2010
DK14.07.2010
FI14.07.2010
IT14.07.2010
NL14.07.2010
SE14.07.2010
TR14.07.2010
IE03.08.2010
LU03.08.2010
CH31.08.2010
LI31.08.2010
MC31.08.2010
FR14.09.2010
GR15.10.2010
ES25.10.2010
PT15.11.2010
[2012/47]
Former [2012/44]AT14.07.2010
BE14.07.2010
CY14.07.2010
DK14.07.2010
FI14.07.2010
IT14.07.2010
NL14.07.2010
SE14.07.2010
IE03.08.2010
LU03.08.2010
CH31.08.2010
LI31.08.2010
MC31.08.2010
FR14.09.2010
GR15.10.2010
ES25.10.2010
PT15.11.2010
Former [2011/35]AT14.07.2010
BE14.07.2010
CY14.07.2010
DK14.07.2010
FI14.07.2010
IT14.07.2010
NL14.07.2010
SE14.07.2010
IE03.08.2010
CH31.08.2010
LI31.08.2010
MC31.08.2010
FR14.09.2010
GR15.10.2010
ES25.10.2010
PT15.11.2010
Former [2011/31]AT14.07.2010
BE14.07.2010
CY14.07.2010
DK14.07.2010
FI14.07.2010
IT14.07.2010
NL14.07.2010
SE14.07.2010
CH31.08.2010
LI31.08.2010
MC31.08.2010
GR15.10.2010
ES25.10.2010
PT15.11.2010
Former [2011/20]AT14.07.2010
BE14.07.2010
CY14.07.2010
DK14.07.2010
FI14.07.2010
NL14.07.2010
SE14.07.2010
CH31.08.2010
LI31.08.2010
MC31.08.2010
GR15.10.2010
PT15.11.2010
Former [2011/19]AT14.07.2010
BE14.07.2010
CY14.07.2010
DK14.07.2010
FI14.07.2010
NL14.07.2010
SE14.07.2010
MC31.08.2010
GR15.10.2010
PT15.11.2010
Former [2011/16]AT14.07.2010
BE14.07.2010
CY14.07.2010
FI14.07.2010
NL14.07.2010
SE14.07.2010
MC31.08.2010
GR15.10.2010
PT15.11.2010
Former [2011/15]AT14.07.2010
CY14.07.2010
FI14.07.2010
NL14.07.2010
SE14.07.2010
MC31.08.2010
GR15.10.2010
PT15.11.2010
Former [2011/13]AT14.07.2010
CY14.07.2010
FI14.07.2010
NL14.07.2010
PT15.11.2010
Former [2011/10]AT14.07.2010
FI14.07.2010
NL14.07.2010
PT15.11.2010
Former [2011/08]AT14.07.2010
NL14.07.2010
Cited inInternational search[A]GB2157519  (SABET COOROSH) [A] 1-10* the whole document *;
 [A]US5638016  (EITRHEIM JOHN K [US]) [A] 1-10 * column 2, line 54 - column 3, line 11 * * column 3, line 53 - column 4, line 8 * * figure 1 *;
 [Y]US5675273  (MASLEID ROBERT PAUL [US]) [Y] 1-10 * column 1, line 65 - column 2, line 9 * * column 2, line 38 - column 5, line 33 * * figures 1-3 *;
 [Y]JP2000013204  (FUJITSU LTD) [Y] 1-10;
 US6191630  [ ] (OZAWA SEIICHI [JP], et al) [ ] * column 3, line 14 - line 65 *;
 [A]  - ANONYMOUS, "CMOS DELAY CIRCUIT", IBM TECH DISCL BULL MAY 1985, (198505), vol. 27, no. 12, pages 7134 - 7135, XP002191214 [A] 1-10 * the whole document *
ExaminationUS6191630
by applicantUS5638016
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.