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Extract from the Register of European Patents

EP About this file: EP1341231

EP1341231 - System and method for providing mechanical planarization of a sequential build up substrate for an integrated circuit package [Right-click to bookmark this link]
StatusThe application has been withdrawn
Status updated on  20.10.2006
Database last updated on 18.05.2024
Most recent event   Tooltip20.10.2006Withdrawal of applicationpublished on 22.11.2006  [2006/47]
Applicant(s)For all designated states
STMicroelectronics, Inc.
1310 Electronics Drive Carrollton
Texas 75006-5039 / US
[N/P]
Former [2003/36]For all designated states
STMicroelectronics, Inc.
1310 Electronics Drive
Carrollton Texas 75006-5039 / US
Inventor(s)01 / Chiu, Anthony M.
2563 Buttercup Drive
Richardson, Texas 75082 / US
02 / Siegel, Harry Michael
825 Wheelwood Drive
Hurst, Texas 76053 / US
 [2003/36]
Representative(s)Style, Kelda Camilla Karen, et al
Page White & Farrer Limited
Bedford House
21A John Street
London WC1N 2BF / GB
[N/P]
Former [2003/36]Style, Kelda Camilla Karen, et al
Page White & Farrer, 54 Doughty Street
London WC1N 2LS / GB
Application number, filing date03250539.829.01.2003
[2003/36]
Priority number, dateUS2002006642231.01.2002         Original published format: US 66422
[2003/36]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP1341231
Date:03.09.2003
Language:EN
[2003/36]
Type: A3 Search report 
No.:EP1341231
Date:19.07.2006
[2006/29]
Search report(s)(Supplementary) European search report - dispatched on:EP16.06.2006
ClassificationIPC:H01L21/48
[2006/29]
CPC:
H01L21/481 (EP,US); H01L21/4857 (EP,US); H05K3/4655 (EP,US);
H01L2224/48091 (EP,US); H01L2224/48227 (EP,US); H01L2224/48237 (EP,US);
H01L2224/73265 (EP,US); H05K2201/0195 (EP,US); H05K2201/09781 (EP,US);
H05K2201/09881 (EP,US); H05K2203/0278 (EP,US); H05K3/4652 (EP,US) (-)
C-Set:
H01L2224/48091, H01L2924/00014 (EP,US)
Former IPC [2003/36]H01L23/522, H01L21/768, H01L21/3105
Designated contracting statesAT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HU,   IE,   IT,   LI,   LU,   MC,   NL,   PT,   SE,   SI,   SK,   TR [2003/36]
Extension statesALNot yet paid
LTNot yet paid
LVNot yet paid
MKNot yet paid
RONot yet paid
TitleGerman:Verfahren und Vorrichtung zum mechanischen Planarisieren von gestapelten Schichten in einem integrierten Schaltungsgehäuse[2003/36]
English:System and method for providing mechanical planarization of a sequential build up substrate for an integrated circuit package[2003/36]
French:Système et méthode de planarisation mechanique d'une superposition de couches dans un boîtier de circuit intégré[2003/36]
Examination procedure10.10.2006Application withdrawn by applicant  [2006/47]
Fees paidRenewal fee
04.11.2004Renewal fee patent year 03
12.01.2006Renewal fee patent year 04
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Documents cited:Search[X]JPH02290095  ;
 [X]JPS63240045  ;
 [X]JPH0766552  (HITACHI LTD) [X] 1-18 * paragraphs [0001] - [0011] * * figure 4 *;
 [X]JPH10256707  (NGK SPARK PLUG CO) [X] 1-8 * paragraph [0015] * * paragraphs [0022] - [0028] - [0039] * * figures 5,6,7E *;
 [A]JP2000332387  (NODA SCREEN KK) [A] 1-3,5,6,9,13 * the whole document *;
 [A]US2002005249  (KUWAKO FUJIO [JP], et al) [A] 1,5,9,13,18 * paragraphs [0031] - [0033] * * paragraphs [0049] , [0050] ** figure 2 *
 [X]  - PATENT ABSTRACTS OF JAPAN, (19910215), vol. 015, no. 066, Database accession no. (E - 1034), & JP02290095 A 19901129 (MATSUSHITA ELECTRIC WORKS LTD) [X] 1-4 * abstract * * figures 1-4 *
 [X]  - PATENT ABSTRACTS OF JAPAN, (19890202), vol. 013, no. 046, Database accession no. (E - 711), & JP63240045 A 19881005 (MATSUSHITA ELECTRIC IND CO LTD) [X] 1-4 * abstract * * figures 1-7 *
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.