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EP2947577
European procedure
Extract from the Register of European Patents
EP About this file: EP2947577
| EP2947577 - INTER-PROCESSOR SYNCHRONIZATION SYSTEM [Right-click to bookmark this link] | Status | The patent has been granted Status updated on 06.10.2023 Database last updated on 24.04.2024 | |
| Former | Grant of patent is intended Status updated on 04.06.2023 | ||
| Former | Examination is in progress Status updated on 05.02.2020 | Most recent event Tooltip | 19.04.2024 | Lapse of the patent in a contracting state New state(s): BG, LT, NL | published on 22.05.2024 [2024/21] | Applicant(s) | For all designated states Kalray 86 Rue de Paris 91400 Orsay / FR | [2023/45] |
| Former [2015/48] | For all designated states Kalray 86 Rue de Paris 91400 Orsay / FR | Inventor(s) | 01 /
Dupont de Dinechin, Benoît 1 pl Hubert Dubedout 38000 Grenoble / FR | 02 /
Ray, Vincent c/o KALRAY 86 Rue de Paris 91400 Orsay / FR | [2015/48] | Representative(s) | de Jong, Jean Jacques, et al Omnipat 610 Chemin de Fabrègues 13510 Éguilles / FR | [N/P] |
| Former [2015/48] | de Jong, Jean Jacques, et al Omnipat 24, place des Martyrs de la Résistance 13100 Aix en Provence / FR | Application number, filing date | 15167601.2 | 13.05.2015 | [2015/48] | Priority number, date | FR20140054591 | 21.05.2014 Original published format: FR 1454591 | [2015/48] | Filing language | FR | Procedural language | FR | Publication | Type: | A1 Application with search report | No.: | EP2947577 | Date: | 25.11.2015 | Language: | FR | [2015/48] | Type: | B1 Patent specification | No.: | EP2947577 | Date: | 08.11.2023 | Language: | FR | [2023/45] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 27.10.2015 | Classification | IPC: | G06F15/173, G06F9/52 | [2015/48] | CPC: |
G06F13/4278 (EP,US);
G06F15/17325 (EP,US);
G06F15/82 (US);
G06F9/30087 (US);
G06F9/52 (EP,US)
| Designated contracting states | AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR [2016/26] |
| Former [2015/48] | AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR | Title | German: | SYNCHRONISATIONSSYSTEM ZWISCHEN PROZESSOREN | [2015/48] | English: | INTER-PROCESSOR SYNCHRONIZATION SYSTEM | [2015/48] | French: | SYSTÈME DE SYNCHRONISATION INTER-PROCESSEURS | [2015/48] | Examination procedure | 23.05.2016 | Amendment by applicant (claims and/or description) | 23.05.2016 | Examination requested [2016/26] | 10.02.2020 | Despatch of a communication from the examining division (Time limit: M06) | 03.08.2020 | Reply to a communication from the examining division | 05.06.2023 | Communication of intention to grant the patent | 02.10.2023 | Fee for grant paid | 02.10.2023 | Fee for publishing/printing paid | 02.10.2023 | Receipt of the translation of the claim(s) | Fees paid | Renewal fee | 18.05.2017 | Renewal fee patent year 03 | 22.05.2018 | Renewal fee patent year 04 | 28.05.2019 | Renewal fee patent year 05 | 25.05.2020 | Renewal fee patent year 06 | 18.05.2021 | Renewal fee patent year 07 | 17.05.2022 | Renewal fee patent year 08 | 15.05.2023 | Renewal fee patent year 09 |
| Opt-out from the exclusive Tooltip competence of the Unified Patent Court | See the Register of the Unified Patent Court for opt-out data | ||
| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | LT | 08.11.2023 | NL | 08.11.2023 | BG | 08.02.2024 | GR | 09.02.2024 | IS | 08.03.2024 | [2024/21] |
| Former [2024/20] | GR | 09.02.2024 | |
| IS | 08.03.2024 | Documents cited: | Search | [IA] - P Gerin, "Modèles de simulation pour la validation logicielle et l'exploration d'architectures des systèmes multiprocesseurs sur puce", Thèse, doi:10.1109/13.214713, (20091130), pages 1 - 142, URL: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=214713, (20150408), XP055181728 [I] 1-3,8-10 * page 11, line 4 - page 13, line l; figure 2.3 * [A] 4-7 DOI: http://dx.doi.org/10.1109/13.214713 | [IA] - CRISTIANO ARAUJO ET AL, "Platform designer: An approach for modeling multiprocessor platforms based on SystemC", DESIGN AUTOMATION FOR EMBEDDED SYSTEMS ; AN INTERNATIONAL JOURNAL, KLUWER ACADEMIC PUBLISHERS, BO, (20051201), vol. 10, no. 4, doi:10.1007/S10617-006-0654-9, ISSN 1572-8080, pages 253 - 283, XP019464684 [I] 1-3,8-10 * page 271, line 3 - page 274, line 8; figures 17, 19 * [A] 4-7 DOI: http://dx.doi.org/10.1007/s10617-006-0654-9 | [IA] - C Koch-Hofer, "Modélisation, Validation et Présynthèse de Circuits Asynchrones en SystemC", HAL Id: tel-00388418, (20090326), pages 1 - 155, URL: http://hal.univ-grenoble-alpes.fr/tel-00388418/document, (20150408), XP055181680 [I] 1-3,8-10 * page 39, line 5 - page 43, line 1 * * figures 2.5, 2.6, 2.7, 2.8 * [A] 4-7 | by applicant | - RAJIV GUPTA, "Employing Register Channels for the Exploitation of Instruction Level Parallelism", PPOPP '90 PROCEEDINGS OF THE SECOND ACM SIGPLAN SYMPOSIUM ON PRINCIPLES & PRACTICE OF PARALLEL PROGRAMMING, pages 118 - 127 |