EP3513293 - SYSTEMS AND METHODS FOR MITIGATING FAULTS IN COMBINATORY LOGIC [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 02.12.2022 Database last updated on 20.09.2024 | |
Former | Grant of patent is intended Status updated on 17.03.2022 | ||
Former | Examination is in progress Status updated on 23.04.2021 | ||
Former | Request for examination was made Status updated on 21.06.2019 | ||
Former | The international publication has been made Status updated on 24.03.2018 | Most recent event Tooltip | 02.12.2022 | Application deemed to be withdrawn | published on 04.01.2023 [2023/01] | Applicant(s) | For all designated states University of Southern California USC Stevens Institute For Innovation 1150 South Olive Street Suite 2300 Los Angeles, CA 90015 / US | [2019/30] | Inventor(s) | 01 /
SIKA, Michel C/O USC Stevens Institute for Innovation 1150 S. Olive Street, Suite 2300 Los Angeles, CA 90015 / US | [2019/34] |
Former [2019/30] | 01 /
SIKA, Michel 3740 McClintock Avenue EEB 500 Los Angeles, California 90089 / US | Representative(s) | Warren, Caroline Elisabeth, et al Mathys & Squire The Shard 32 London Bridge Street London SE1 9SG / GB | [N/P] |
Former [2019/30] | Warren, Caroline Elisabeth, et al Mathys & Squire LLP The Shard 32 London Bridge Street London SE1 9SG / GB | Application number, filing date | 17851658.9 | 15.09.2017 | [2019/30] | WO2017US51903 | Priority number, date | US201662395992P | 16.09.2016 Original published format: US 201662395992 P | [2019/30] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | WO2018053346 | Date: | 22.03.2018 | Language: | EN | [2018/12] | Type: | A1 Application with search report | No.: | EP3513293 | Date: | 24.07.2019 | Language: | EN | The application published by WIPO in one of the EPO official languages on 22.03.2018 takes the place of the publication of the European patent application. | [2019/30] | Search report(s) | International search report - published on: | US | 22.03.2018 | (Supplementary) European search report - dispatched on: | EP | 20.04.2020 | Classification | IPC: | G06F11/00, G06F11/07, G06F11/16, G06F11/18, G06F11/10 | [2020/21] | CPC: |
G06F11/00 (EP,US);
G06F11/104 (EP,US);
G06F11/0793 (EP);
G06F11/1024 (EP,US);
G06F11/1608 (EP);
G06F11/1629 (EP);
G06F11/1641 (EP);
G06F11/18 (EP);
G06F30/327 (EP,US);
|
Former IPC [2019/30] | G06F11/00 | Designated contracting states | AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR [2019/30] | Title | German: | SYSTEME UND VERFAHREN ZUR ABSCHWÄCHUNG VON FEHLERN IN KOMBINATORISCHER LOGIK | [2019/30] | English: | SYSTEMS AND METHODS FOR MITIGATING FAULTS IN COMBINATORY LOGIC | [2019/30] | French: | SYSTÈMES ET PROCÉDÉS PERMETTANT D'ATTÉNUER DES DÉFAUTS DANS UNE LOGIQUE COMBINATOIRE | [2019/30] | Entry into regional phase | 04.03.2019 | National basic fee paid | 04.03.2019 | Search fee paid | 04.03.2019 | Designation fee(s) paid | 04.03.2019 | Examination fee paid | Examination procedure | 04.03.2019 | Examination requested [2019/30] | 12.11.2020 | Amendment by applicant (claims and/or description) | 26.04.2021 | Despatch of a communication from the examining division (Time limit: M04) | 06.09.2021 | Reply to a communication from the examining division | 18.03.2022 | Communication of intention to grant the patent | 29.07.2022 | Application deemed to be withdrawn, date of legal effect [2023/01] | 19.08.2022 | Despatch of communication that the application is deemed to be withdrawn, reason: fee for grant / fee for printing not paid in time [2023/01] | Fees paid | Renewal fee | 25.09.2019 | Renewal fee patent year 03 | 25.09.2020 | Renewal fee patent year 04 | 28.09.2021 | Renewal fee patent year 05 | Penalty fee | Additional fee for renewal fee | 30.09.2022 | 06   M06   Not yet paid |
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]US4924467 (CRISWELL PETER B [US]) [A] 1-12 * abstract * * column 2, lines 21-54 * * column 2, line 66 - column 3, line 15 * * column 3, line 27 - column 4, line 14 ** column 5, line 12 - column 7, line 30 *; | [I] - M. D. Sika ET AL, "Applying Residue Arithmetic Codes to Combinational Logic to Reduce Single Event Upsets", (20140416), URL: https://www.cc.gatech.edu/-ayazdanb/pubtication/papers/residue-radecs13.pdf, (20180806), XP055497557 [I] 1-12 * abstract * * page 1 - page 2 * | International search | [A]US6963217 (SAMUDRALA PRAVEEN K [US], et al) [A] 1-20 * entire document *; | [A]US7036059 (CARMICHAEL CARL H [US], et al) [A] 1-20 * entire document *; | [A]US7035891 (MAKINENI SIVAKUMAR [US], et al) [A] 1-20 * entire document *; | [A]US7260742 (CZAJKOWSKI DAVID R [US]) [A] 1-20 * entire document *; | [A]US2011013768 (LAMBERT ROBERT JOHN [CA]) [A] 1-20* entire document *; | [A]US8489919 (CLARK LAWRENCE T [US], et al) [A] 1-20 * (col. 1, In 30-33; col. 4, In 17-23; col. 12, In 58; col. 17, In 61-62) *; | [A]US2015277855 (SHIN JONGHOON [KR], et al) [A] 1-20 * entire document *; | [A] - SIKA, M. D. et al., "Applying Residue Arithmetic Codes to Combinational Logic to Reduce Single Event Upsets", (20140416), URL: https://www.cc.gatech.edu/-ayazdanb/pubtication/papers/residue-radecs13.pdf, (20171113), XP055497557 [A] 1-20 * (pg. 1, col. 1 and col. 2; pg. 2, col. 1 and col. 2 ; pg. 3, col. 1; pg. 4, col. 2; Fig. 1, Fig. 2). * | [A] - BOLCHINI et al., "TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs", Defect and Fault-Tolerance in VLSI Systems , 2007. DFT'07. 22nd IEEE International Symposium, (20070000), URL: https://pdfs.semanticscholar.org/f6f4/8adba7b71a93cb4b1d591f051a6c9dd37c5e.pdf, (20171113), XP031337801 [A] 1-20 * entire document * | [A] - SIKA, MICHEL D. et al., Low Energy Hardening of Combinatorial Logic using Standard Cells and Residue Codes, (20140416), URL: https://www.cc.gatech.edu/-ayazdanb/ publication/papers/residue-gomactech14pdf, (20171113), XP055497559 [A] 1-20 * entire document * | [L] - Index of /~ayazdanb/publication/papers, URL: https://www.cc.gatech.edu/-ayazdanb/publication/papers, (20171113) [L] 1-20 * (cites publication dates for both Sika references) * | by applicant | US4924467 | - M.D. SIKA, Applying Residue Arithmetic Codes to Combinational Logic to Reduce Single Event Upsets |