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EP0067304
European procedure
Extract from the Register of European Patents
EP About this file: EP0067304
| EP0067304 - Processing array and method for the physical design of very large scale integrated circuits [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 30.11.1989 Database last updated on 20.05.2024 | Most recent event Tooltip | 17.04.2015 | Change - lapse in a contracting state Updated state(s): BE | published on 20.05.2015 [2015/21] | Applicant(s) | For all designated states International Business Machines Corporation New Orchard Road Armonk, NY 10504 / US | [N/P] |
| Former [1982/51] | For all designated states International Business Machines Corporation Old Orchard Road Armonk, N.Y. 10504 / US | Inventor(s) | 01 /
Hong, Se June 1374 White Hill Road Yorktown Heights New York 10598 / US | 02 /
Nair, Ravindra Kumar 5G Hillcrest Park Peekskill New York 10566 / US | 03 /
Shapiro, Eugene 138 West Haviland Lane Stamford Conn. 06903 / US | [1982/51] | Representative(s) | Blakemore, Frederick Norman IBM United Kingdom Limited Intellectual Property Department Hursley Park Winchester Hampshire SO21 2JN / GB | [N/P] |
| Former [1989/48] | Blakemore, Frederick Norman IBM United Kingdom Limited Intellectual Property Department Hursley Park Winchester Hampshire SO21 2JN / GB | ||
| Former [1986/17] | Appleton, John Edward IBM United Kingdom Limited Intellectual Property Department Hursley Park Winchester Hampshire SO21 2JN / GB | ||
| Former [1982/51] | Lancaster, James Donald IBM United Kingdom Patent Operations Hursley Park Winchester, Hants, S021 2JN / GB | Application number, filing date | 82103941.9 | 06.05.1982 | [1982/51] | Priority number, date | US19810272880 | 12.06.1981 Original published format: US 272880 | [1982/51] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0067304 | Date: | 22.12.1982 | Language: | EN | [1982/51] | Type: | A3 Search report | No.: | EP0067304 | Date: | 25.07.1984 | Language: | EN | [1984/30] | Type: | B1 Patent specification | No.: | EP0067304 | Date: | 01.02.1989 | Language: | EN | [1989/05] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 21.05.1984 | Classification | IPC: | G06F15/60 | [1989/05] | CPC: |
G06F30/394 (EP,US)
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| Former IPC [1982/51] | G06F15/20 | Designated contracting states | BE, DE, FR, GB, IT [1982/51] | Title | German: | Verarbeitungsnetz und Verfahren zur physischen Planung von in sehr hohem Grad integrierten Schaltkreisen | [1982/51] | English: | Processing array and method for the physical design of very large scale integrated circuits | [1982/51] | French: | Réseau de calcul et méthode pour la planification physique de circuits intégrés à très grande échelle | [1982/51] | Examination procedure | 20.04.1983 | Examination requested [1983/26] | 17.01.1986 | Despatch of a communication from the examining division (Time limit: M06) | 30.06.1986 | Reply to a communication from the examining division | 17.07.1987 | Despatch of a communication from the examining division (Time limit: M06) | 07.01.1988 | Reply to a communication from the examining division | 16.05.1988 | Despatch of communication of intention to grant (Approval: Yes) | 27.07.1988 | Communication of intention to grant the patent | 06.08.1988 | Fee for grant paid | 06.08.1988 | Fee for publishing/printing paid | Opposition(s) | 03.11.1989 | No opposition filed within time limit [1990/03] | Fees paid | Renewal fee | 23.05.1984 | Renewal fee patent year 03 | 24.05.1985 | Renewal fee patent year 04 | 23.05.1986 | Renewal fee patent year 05 | 29.05.1987 | Renewal fee patent year 06 | 31.05.1988 | Renewal fee patent year 07 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | BE | 01.02.1989 | [2015/21] |
| Former [1989/39] | BE | 31.05.1989 | Documents cited: | Search | [A]US4065808 (SCHOMBERG HERMANN, et al); | [AD]US3979728 (REDDAWAY STEWART FIDDIAN) | [A] - ASSOCIAZIONE ELETTROTECNICA ED ELETTRONICA ITALIANA, Rendiconti delle LXVII riunione annuale, Alghero, 1966, Extra issue of "L'ELETTROTECNICA", pages II-84 1-8, Milano (IT); L. GILLI et al.: "II-84/1966 - Elaboratore speciale per la sintesi di circuiti logici combinatori". | [A] - IEEE INTERNATIONAL CONFERENCE ON CIRCUITS AND COMPUTERS, ICCC 80, 1st-3rd October 1980, pages 207-209, Port Chester N.Y. (USA); D. KATZ: "Gate array chips and computer aided design methods for custom LSI/VLSI". |