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EP0329418
European procedure
Extract from the Register of European Patents
EP About this file: EP0329418
| EP0329418 - Circuit synchronization system [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 26.04.1996 Database last updated on 15.05.2024 | Most recent event Tooltip | 30.10.2009 | Change - representative | published on 02.12.2009 [2009/49] | Applicant(s) | For all designated states SILICON GRAPHICS, INC. 2011 N. Shoreline Boulevard Mountain View, CA 94039-7311 / US | [1995/08] |
| Former [1989/34] | For all designated states MIPS COMPUTER SYSTEMS, INC. 930 Arques Avenue Sunnyvale, California 94086-3650 / US | Inventor(s) | 01 /
Johnson, Mark G. 1000 Escalon No.112 Sunnyvale California 94086 / US | 02 /
Hudson, Edwin L. 364 Dayton Avenue Santa Clara California 95051 / US | [1989/34] | Representative(s) | Freeman, Jacqueline Carol, et al WP Thompson 138 Fetter Lane London EC4A 1BT / GB | [N/P] |
| Former [2009/49] | Freeman, Jacqueline Carol, et al W.P.Thompson & Co. 55 Drury Lane London WC2B 5SQ / GB | ||
| Former [1995/08] | Freeman, Jacqueline Carol, et al W.P. THOMPSON & CO. Celcon House 289-293 High Holborn London WC1V 7HU / GB | ||
| Former [1994/35] | Jones, Ian W.P. THOMPSON & CO. Celcon House 289-293 High Holborn London WC1V 7HU / GB | ||
| Former [1989/34] | Jones, Ian W.P. THOMPSON & CO. Celcon House 289-293 High Holborn London WC1V 7HU / GB | Application number, filing date | 89301447.2 | 15.02.1989 | [1989/34] | Priority number, date | US19880156779 | 17.02.1988 Original published format: US 156779 | [1989/34] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0329418 | Date: | 23.08.1989 | Language: | EN | [1989/34] | Type: | A3 Search report | No.: | EP0329418 | Date: | 06.11.1991 | Language: | EN | [1991/45] | Type: | B1 Patent specification | No.: | EP0329418 | Date: | 21.06.1995 | Language: | EN | [1995/25] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 18.09.1991 | Classification | IPC: | H03L7/00, G06F1/04 | [1991/45] | CPC: |
H03L7/0812 (EP,US);
G06F7/00 (KR);
G06F1/10 (EP)
|
| Former IPC [1989/34] | G06F1/04, H03L7/00 | Designated contracting states | DE, FR, GB, IT, NL [1989/34] | Title | German: | Schaltungssynchronisationssystem | [1989/34] | English: | Circuit synchronization system | [1989/34] | French: | Système de synchronisation de circuits | [1989/34] | Examination procedure | 05.05.1992 | Examination requested [1992/28] | 22.11.1993 | Despatch of communication of intention to grant (Approval: No) | 30.05.1994 | Despatch of communication of intention to grant (Approval: later approval) | 10.06.1994 | Communication of intention to grant the patent | 09.09.1994 | Fee for grant paid | 09.09.1994 | Fee for publishing/printing paid | Opposition(s) | 22.03.1996 | No opposition filed within time limit [1996/24] | Fees paid | Renewal fee | 15.02.1991 | Renewal fee patent year 03 | 10.02.1992 | Renewal fee patent year 04 | 23.02.1993 | Renewal fee patent year 05 | 24.02.1994 | Renewal fee patent year 06 | 23.01.1995 | Renewal fee patent year 07 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | NL | 21.06.1995 | [2003/07] | Documents cited: | Search | [A]GB2127594 (INT COMPUTERS LTD) | [XP] - IEEE INTERNATIONAL SOLID STATE CIRCUITS CONFERENCE. vol. 31, 1988, 17-19 FEBR.,NEW YORK US pages 142 - 143; MARK G.JOHNSON: 'A variable delay line phase locked loop for CPU-CoProcessor Synchronization ' |