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EP1040482
European procedure
Extract from the Register of European Patents
EP About this file: EP1040482
| EP1040482 - INTEGRATED-CIRCUIT MEMORY WITH A BUFFER CIRCUIT [Right-click to bookmark this link] | |||
| Former [2000/40] | BUFFER CIRCUIT AND INTEGRATED-CIRCUIT MEMORY WITH A BUFFER CIRCUIT | ||
| [2001/10] | Status | No opposition filed within time limit Status updated on 16.08.2002 Database last updated on 23.04.2024 | Most recent event Tooltip | 16.08.2002 | No opposition filed within time limit | published on 02.10.2002 [2002/40] | Applicant(s) | For all designated states Infineon Technologies AG St.-Martin-Strasse 53 81669 München / DE | [2001/41] |
| Former [2000/40] | For all designated states Infineon Technologies AG St.-Martin-Strasse 53 81541 München / DE | Inventor(s) | 01 /
SAVIGNAC, Dominique Bahnhofstrasse 2 D-85737 Ismaning / DE | 02 /
FEURLE, Robert Haringstrasse 47 D-85635 Höhenkirchen / DE | 03 /
SCHNEIDER, Helmut Dachauer Strasse 314 D-80993 München / DE | [2000/40] | Representative(s) | Zedlitz, Peter, et al OSRAM GmbH Intellectual Property IP Postfach 22 13 17 80503 München / DE | [N/P] |
| Former [2001/18] | Zedlitz, Peter, Dipl.-Inf., et al Patentanwalt, Postfach 22 13 17 80503 München / DE | Application number, filing date | 98961078.7 | 11.11.1998 | [2000/40] | WO1998DE03306 | Priority number, date | DE1997155737 | 15.12.1997 Original published format: DE 19755737 | [2000/40] | Filing language | DE | Procedural language | DE | Publication | Type: | A1 Application with search report | No.: | WO9931664 | Date: | 24.06.1999 | Language: | DE | [1999/25] | Type: | A1 Application with search report | No.: | EP1040482 | Date: | 04.10.2000 | Language: | DE | The application published by WIPO in one of the EPO official languages on 24.06.1999 takes the place of the publication of the European patent application. | [2000/40] | Type: | B1 Patent specification | No.: | EP1040482 | Date: | 10.10.2001 | Language: | DE | [2001/41] | Search report(s) | International search report - published on: | EP | 24.06.1999 | Classification | IPC: | G11C5/14, H02J9/06 | [2000/40] | CPC: |
G11C11/4074 (EP,US);
G11C5/14 (KR);
G11C5/141 (EP,US);
H02J9/061 (EP,US)
| Designated contracting states | DE, FR, GB, IE, IT [2000/40] | Title | German: | INTEGRIERTE SPEICHERSCHALTUNG MIT EINER PUFFERSCHALTUNG | [2001/10] | English: | INTEGRATED-CIRCUIT MEMORY WITH A BUFFER CIRCUIT | [2001/10] | French: | CIRCUIT INTEGRE DE MEMOIRE DOTE D'UN CIRCUIT DE TAMPON | [2001/10] |
| Former [2000/40] | PUFFERSCHALTUNG UND INTEGRIERTE SPEICHERSCHALTUNG MIT EINER PUFFERSCHALTUNG | ||
| Former [2000/40] | BUFFER CIRCUIT AND INTEGRATED-CIRCUIT MEMORY WITH A BUFFER CIRCUIT | ||
| Former [2000/40] | CIRCUIT DE TAMPON ET CIRCUIT INTEGRE DE MEMOIRE DOTE D'UN CIRCUIT DE TAMPON | Entry into regional phase | 17.04.2000 | National basic fee paid | 17.04.2000 | Designation fee(s) paid | 17.04.2000 | Examination fee paid | Examination procedure | 15.06.1999 | Request for preliminary examination filed International Preliminary Examining Authority: EP | 17.04.2000 | Examination requested [2000/40] | 08.02.2001 | Despatch of communication of intention to grant (Approval: Yes) | 29.03.2001 | Communication of intention to grant the patent | 19.04.2001 | Fee for grant paid | 19.04.2001 | Fee for publishing/printing paid | Opposition(s) | 11.07.2002 | No opposition filed within time limit [2002/40] | Fees paid | Renewal fee | 20.11.2000 | Renewal fee patent year 03 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Cited in | International search | [A]JPS63257088 ; | [A]JPH05276683 ; | [X]JPH05284670 ; | [A]JPH02292797 ; | [A]US3753001 (HIROSHIMA M, et al) [A] 1,2* column 2, line 61 - column 5, line 19; figure 3 *; | [X] - "ACTIVE LOW DISSIPATION POWER SUPPLY REGULATOR", IBM TECHNICAL DISCLOSURE BULLETIN., NEW YORK US, (196909), vol. 12, no. 4, page 515, XP002103045 [X] 1-3,8,10 * the whole document * | [A] - PATENT ABSTRACTS OF JAPAN, (19890220), vol. 013, no. 073, Database accession no. (P - 830), & JP63257088 A 19881024 (NEC CORP) [A] 1,2 * abstract * | [A] - PATENT ABSTRACTS OF JAPAN, (19940131), vol. 018, no. 060, Database accession no. (E - 1499), & JP05276683 A 19931022 (MATSUSHITA ELECTRIC WORKS LTD) [A] 4,6 * abstract * | [X] - PATENT ABSTRACTS OF JAPAN, (19940207), vol. 018, no. 073, Database accession no. (E - 1503), & JP05284670 A 19931029 (NEC CORP) [X] 1,2 * abstract * | [A] - PATENT ABSTRACTS OF JAPAN, (19910219), vol. 015, no. 071, Database accession no. (P - 1168), & JP02292797 A 19901204 (HITACHI LTD;OTHERS: 01) [A] 1,2 * abstract * |